irqchip/gicv3: Workaround for NVIDIA erratum T241-FABRIC-4
The T241 platform suffers from the T241-FABRIC-4 erratum which causes
unexpected behavior in the GIC when multiple transactions are received
simultaneously from different sources. This hardware issue impacts
NVIDIA server platforms that use more than two T241 chips
interconnected. Each chip has support for 320 {E}SPIs.
This issue occurs when multiple packets from different GICs are
incorrectly interleaved at the target chip. The erratum text below
specifies exactly what can cause multiple transfer packets susceptible
to interleaving and GIC state corruption. GIC state corruption can
lead to a range of problems, including kernel panics, and unexpected
behavior.
>From the erratum text:
"In some cases, inter-socket AXI4 Stream packets with multiple
transfers, may be interleaved by the fabric when presented to ARM
Generic Interrupt Controller. GIC expects all transfers of a packet
to be delivered without any interleaving.
The following GICv3 commands may result in multiple transfer packets
over inter-socket AXI4 Stream interface:
- Register reads from GICD_I* and GICD_N*
- Register writes to 64-bit GICD registers other than GICD_IROUTERn*
- ITS command MOVALL
Multiple commands in GICv4+ utilize multiple transfer packets,
including VMOVP, VMOVI, VMAPP, and 64-bit register accesses."
This issue impacts system configurations with more than 2 sockets,
that require multi-transfer packets to be sent over inter-socket
AXI4 Stream interface between GIC instances on different sockets.
GICv4 cannot be supported. GICv3 SW model can only be supported
with the workaround. Single and Dual socket configurations are not
impacted by this issue and support GICv3 and GICv4."
Link: https://developer.nvidia.com/docs/t241-fabric-4/nvidia-t241-fabric-4-errata.pdf
Writing to the chip alias region of the GICD_In{E} registers except
GICD_ICENABLERn has an equivalent effect as writing to the global
distributor. The SPI interrupt deactivate path is not impacted by
the erratum.
To fix this problem, implement a workaround that ensures read accesses
to the GICD_In{E} registers are directed to the chip that owns the
SPI, and disable GICv4.x features. To simplify code changes, the
gic_configure_irq() function uses the same alias region for both read
and write operations to GICD_ICFGR.
Co-developed-by: Vikram Sethi <vsethi@nvidia.com>
Signed-off-by: Vikram Sethi <vsethi@nvidia.com>
Signed-off-by: Shanker Donthineni <sdonthineni@nvidia.com>
Acked-by: Sudeep Holla <sudeep.holla@arm.com> (for SMCCC/SOC ID bits)
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20230319024314.3540573-2-sdonthineni@nvidia.com
This commit is contained in:
Shanker Donthineni
Marc Zyngier
parent
dee234032e
commit
35727af2b1
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@ -172,6 +172,8 @@ stable kernels.
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+----------------+-----------------+-----------------+-----------------------------+
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| NVIDIA | Carmel Core | N/A | NVIDIA_CARMEL_CNP_ERRATUM |
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+----------------+-----------------+-----------------+-----------------------------+
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| NVIDIA | T241 GICv3/4.x | T241-FABRIC-4 | N/A |
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+----------------+-----------------+-----------------+-----------------------------+
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+----------------+-----------------+-----------------+-----------------------------+
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| Freescale/NXP | LS2080A/LS1043A | A-008585 | FSL_ERRATUM_A008585 |
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+----------------+-----------------+-----------------+-----------------------------+
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@ -17,9 +17,13 @@ static enum arm_smccc_conduit smccc_conduit = SMCCC_CONDUIT_NONE;
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bool __ro_after_init smccc_trng_available = false;
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u64 __ro_after_init smccc_has_sve_hint = false;
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s32 __ro_after_init smccc_soc_id_version = SMCCC_RET_NOT_SUPPORTED;
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s32 __ro_after_init smccc_soc_id_revision = SMCCC_RET_NOT_SUPPORTED;
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void __init arm_smccc_version_init(u32 version, enum arm_smccc_conduit conduit)
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{
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struct arm_smccc_res res;
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smccc_version = version;
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smccc_conduit = conduit;
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@ -27,6 +31,18 @@ void __init arm_smccc_version_init(u32 version, enum arm_smccc_conduit conduit)
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if (IS_ENABLED(CONFIG_ARM64_SVE) &&
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smccc_version >= ARM_SMCCC_VERSION_1_3)
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smccc_has_sve_hint = true;
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if ((smccc_version >= ARM_SMCCC_VERSION_1_2) &&
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(smccc_conduit != SMCCC_CONDUIT_NONE)) {
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arm_smccc_1_1_invoke(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
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ARM_SMCCC_ARCH_SOC_ID, &res);
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if ((s32)res.a0 >= 0) {
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arm_smccc_1_1_invoke(ARM_SMCCC_ARCH_SOC_ID, 0, &res);
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smccc_soc_id_version = (s32)res.a0;
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arm_smccc_1_1_invoke(ARM_SMCCC_ARCH_SOC_ID, 1, &res);
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smccc_soc_id_revision = (s32)res.a0;
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}
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}
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}
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enum arm_smccc_conduit arm_smccc_1_1_get_conduit(void)
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@ -44,6 +60,16 @@ u32 arm_smccc_get_version(void)
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}
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EXPORT_SYMBOL_GPL(arm_smccc_get_version);
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s32 arm_smccc_get_soc_id_version(void)
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{
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return smccc_soc_id_version;
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}
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s32 arm_smccc_get_soc_id_revision(void)
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{
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return smccc_soc_id_revision;
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}
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static int __init smccc_devices_init(void)
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{
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struct platform_device *pdev;
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@ -42,41 +42,23 @@ static int __init smccc_soc_init(void)
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if (arm_smccc_get_version() < ARM_SMCCC_VERSION_1_2)
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return 0;
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if (arm_smccc_1_1_get_conduit() == SMCCC_CONDUIT_NONE) {
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pr_err("%s: invalid SMCCC conduit\n", __func__);
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return -EOPNOTSUPP;
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}
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arm_smccc_1_1_invoke(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
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ARM_SMCCC_ARCH_SOC_ID, &res);
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if ((int)res.a0 == SMCCC_RET_NOT_SUPPORTED) {
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soc_id_version = arm_smccc_get_soc_id_version();
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if (soc_id_version == SMCCC_RET_NOT_SUPPORTED) {
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pr_info("ARCH_SOC_ID not implemented, skipping ....\n");
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return 0;
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}
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if ((int)res.a0 < 0) {
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pr_info("ARCH_FEATURES(ARCH_SOC_ID) returned error: %lx\n",
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res.a0);
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return -EINVAL;
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}
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arm_smccc_1_1_invoke(ARM_SMCCC_ARCH_SOC_ID, 0, &res);
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if ((int)res.a0 < 0) {
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if (soc_id_version < 0) {
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pr_err("ARCH_SOC_ID(0) returned error: %lx\n", res.a0);
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return -EINVAL;
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}
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soc_id_version = res.a0;
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arm_smccc_1_1_invoke(ARM_SMCCC_ARCH_SOC_ID, 1, &res);
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if ((int)res.a0 < 0) {
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soc_id_rev = arm_smccc_get_soc_id_revision();
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if (soc_id_rev < 0) {
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pr_err("ARCH_SOC_ID(1) returned error: %lx\n", res.a0);
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return -EINVAL;
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}
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soc_id_rev = res.a0;
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soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
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if (!soc_dev_attr)
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return -ENOMEM;
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@ -36,6 +36,7 @@ config ARM_GIC_V3
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select IRQ_DOMAIN_HIERARCHY
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select PARTITION_PERCPU
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select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
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select HAVE_ARM_SMCCC_DISCOVERY
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config ARM_GIC_V3_ITS
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bool
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@ -24,6 +24,9 @@
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#include <linux/irqchip/arm-gic-common.h>
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#include <linux/irqchip/arm-gic-v3.h>
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#include <linux/irqchip/irq-partition-percpu.h>
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#include <linux/bitfield.h>
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#include <linux/bits.h>
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#include <linux/arm-smccc.h>
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#include <asm/cputype.h>
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#include <asm/exception.h>
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@ -47,6 +50,7 @@ struct redist_region {
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struct gic_chip_data {
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struct fwnode_handle *fwnode;
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phys_addr_t dist_phys_base;
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void __iomem *dist_base;
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struct redist_region *redist_regions;
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struct rdists rdists;
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@ -59,6 +63,10 @@ struct gic_chip_data {
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struct partition_desc **ppi_descs;
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};
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#define T241_CHIPS_MAX 4
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static void __iomem *t241_dist_base_alias[T241_CHIPS_MAX] __read_mostly;
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static DEFINE_STATIC_KEY_FALSE(gic_nvidia_t241_erratum);
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static struct gic_chip_data gic_data __read_mostly;
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static DEFINE_STATIC_KEY_TRUE(supports_deactivate_key);
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@ -179,6 +187,39 @@ static inline bool gic_irq_in_rdist(struct irq_data *d)
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}
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}
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static inline void __iomem *gic_dist_base_alias(struct irq_data *d)
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{
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if (static_branch_unlikely(&gic_nvidia_t241_erratum)) {
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irq_hw_number_t hwirq = irqd_to_hwirq(d);
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u32 chip;
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/*
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* For the erratum T241-FABRIC-4, read accesses to GICD_In{E}
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* registers are directed to the chip that owns the SPI. The
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* the alias region can also be used for writes to the
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* GICD_In{E} except GICD_ICENABLERn. Each chip has support
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* for 320 {E}SPIs. Mappings for all 4 chips:
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* Chip0 = 32-351
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* Chip1 = 352-671
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* Chip2 = 672-991
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* Chip3 = 4096-4415
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*/
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switch (__get_intid_range(hwirq)) {
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case SPI_RANGE:
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chip = (hwirq - 32) / 320;
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break;
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case ESPI_RANGE:
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chip = 3;
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break;
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default:
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unreachable();
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}
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return t241_dist_base_alias[chip];
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}
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return gic_data.dist_base;
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}
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static inline void __iomem *gic_dist_base(struct irq_data *d)
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{
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switch (get_intid_range(d)) {
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@ -337,7 +378,7 @@ static int gic_peek_irq(struct irq_data *d, u32 offset)
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if (gic_irq_in_rdist(d))
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base = gic_data_rdist_sgi_base();
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else
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base = gic_data.dist_base;
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base = gic_dist_base_alias(d);
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return !!(readl_relaxed(base + offset + (index / 32) * 4) & mask);
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}
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@ -588,7 +629,7 @@ static int gic_set_type(struct irq_data *d, unsigned int type)
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if (gic_irq_in_rdist(d))
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base = gic_data_rdist_sgi_base();
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else
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base = gic_data.dist_base;
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base = gic_dist_base_alias(d);
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offset = convert_offset_index(d, GICD_ICFGR, &index);
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@ -1708,6 +1749,43 @@ static bool gic_enable_quirk_hip06_07(void *data)
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return false;
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}
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#define T241_CHIPN_MASK GENMASK_ULL(45, 44)
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#define T241_CHIP_GICDA_OFFSET 0x1580000
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#define SMCCC_SOC_ID_T241 0x036b0241
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static bool gic_enable_quirk_nvidia_t241(void *data)
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{
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s32 soc_id = arm_smccc_get_soc_id_version();
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unsigned long chip_bmask = 0;
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phys_addr_t phys;
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u32 i;
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/* Check JEP106 code for NVIDIA T241 chip (036b:0241) */
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if ((soc_id < 0) || (soc_id != SMCCC_SOC_ID_T241))
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return false;
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/* Find the chips based on GICR regions PHYS addr */
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for (i = 0; i < gic_data.nr_redist_regions; i++) {
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chip_bmask |= BIT(FIELD_GET(T241_CHIPN_MASK,
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(u64)gic_data.redist_regions[i].phys_base));
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}
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if (hweight32(chip_bmask) < 3)
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return false;
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/* Setup GICD alias regions */
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for (i = 0; i < ARRAY_SIZE(t241_dist_base_alias); i++) {
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if (chip_bmask & BIT(i)) {
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phys = gic_data.dist_phys_base + T241_CHIP_GICDA_OFFSET;
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phys |= FIELD_PREP(T241_CHIPN_MASK, i);
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t241_dist_base_alias[i] = ioremap(phys, SZ_64K);
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WARN_ON_ONCE(!t241_dist_base_alias[i]);
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}
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}
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static_branch_enable(&gic_nvidia_t241_erratum);
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return true;
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}
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static const struct gic_quirk gic_quirks[] = {
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{
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.desc = "GICv3: Qualcomm MSM8996 broken firmware",
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@ -1739,6 +1817,12 @@ static const struct gic_quirk gic_quirks[] = {
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.mask = 0xe8f00fff,
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.init = gic_enable_quirk_cavium_38539,
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},
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{
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.desc = "GICv3: NVIDIA erratum T241-FABRIC-4",
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.iidr = 0x0402043b,
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.mask = 0xffffffff,
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.init = gic_enable_quirk_nvidia_t241,
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},
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{
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}
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};
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@ -1798,7 +1882,8 @@ static void gic_enable_nmi_support(void)
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gic_chip.flags |= IRQCHIP_SUPPORTS_NMI;
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}
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static int __init gic_init_bases(void __iomem *dist_base,
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static int __init gic_init_bases(phys_addr_t dist_phys_base,
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void __iomem *dist_base,
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struct redist_region *rdist_regs,
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u32 nr_redist_regions,
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u64 redist_stride,
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@ -1814,6 +1899,7 @@ static int __init gic_init_bases(void __iomem *dist_base,
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pr_info("GIC: Using split EOI/Deactivate mode\n");
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gic_data.fwnode = handle;
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gic_data.dist_phys_base = dist_phys_base;
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gic_data.dist_base = dist_base;
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gic_data.redist_regions = rdist_regs;
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gic_data.nr_redist_regions = nr_redist_regions;
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@ -1841,10 +1927,13 @@ static int __init gic_init_bases(void __iomem *dist_base,
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gic_data.domain = irq_domain_create_tree(handle, &gic_irq_domain_ops,
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&gic_data);
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gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist));
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if (!static_branch_unlikely(&gic_nvidia_t241_erratum)) {
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/* Disable GICv4.x features for the erratum T241-FABRIC-4 */
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gic_data.rdists.has_rvpeid = true;
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gic_data.rdists.has_vlpis = true;
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gic_data.rdists.has_direct_lpi = true;
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gic_data.rdists.has_vpend_valid_dirty = true;
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}
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if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) {
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err = -ENOMEM;
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@ -2050,6 +2139,7 @@ static void __iomem *gic_of_iomap(struct device_node *node, int idx,
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static int __init gic_of_init(struct device_node *node, struct device_node *parent)
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{
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phys_addr_t dist_phys_base;
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void __iomem *dist_base;
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struct redist_region *rdist_regs;
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struct resource res;
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@ -2063,6 +2153,8 @@ static int __init gic_of_init(struct device_node *node, struct device_node *pare
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return PTR_ERR(dist_base);
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}
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dist_phys_base = res.start;
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err = gic_validate_dist_version(dist_base);
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if (err) {
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pr_err("%pOF: no distributor detected, giving up\n", node);
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@ -2094,8 +2186,8 @@ static int __init gic_of_init(struct device_node *node, struct device_node *pare
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gic_enable_of_quirks(node, gic_quirks, &gic_data);
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err = gic_init_bases(dist_base, rdist_regs, nr_redist_regions,
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redist_stride, &node->fwnode);
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err = gic_init_bases(dist_phys_base, dist_base, rdist_regs,
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nr_redist_regions, redist_stride, &node->fwnode);
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if (err)
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goto out_unmap_rdist;
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@ -2411,8 +2503,9 @@ gic_acpi_init(union acpi_subtable_headers *header, const unsigned long end)
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goto out_redist_unmap;
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}
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err = gic_init_bases(acpi_data.dist_base, acpi_data.redist_regs,
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acpi_data.nr_redist_regions, 0, gsi_domain_handle);
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err = gic_init_bases(dist->base_address, acpi_data.dist_base,
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acpi_data.redist_regs, acpi_data.nr_redist_regions,
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0, gsi_domain_handle);
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if (err)
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goto out_fwhandle_free;
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@ -226,6 +226,24 @@ void __init arm_smccc_version_init(u32 version, enum arm_smccc_conduit conduit);
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extern u64 smccc_has_sve_hint;
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/**
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* arm_smccc_get_soc_id_version()
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*
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* Returns the SOC ID version.
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*
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* When ARM_SMCCC_ARCH_SOC_ID is not present, returns SMCCC_RET_NOT_SUPPORTED.
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*/
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s32 arm_smccc_get_soc_id_version(void);
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/**
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* arm_smccc_get_soc_id_revision()
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*
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* Returns the SOC ID revision.
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*
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* When ARM_SMCCC_ARCH_SOC_ID is not present, returns SMCCC_RET_NOT_SUPPORTED.
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*/
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s32 arm_smccc_get_soc_id_revision(void);
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/**
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* struct arm_smccc_res - Result from SMC/HVC call
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* @a0-a3 result values from registers 0 to 3
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