Updates for the interrupt subsystem:
- Core:
- Make affinity changes immediately effective for interrupt
threads. This reduces the impact on isolated CPUs as it pulls over the
thread right away instead of doing it after the next hardware
interrupt arrived.
- Cleanup and improvements for the interrupt chip simulator
- Deduplication of the interrupt descriptor initialization code so the
sparse and non-sparse mode share more code.
- Drivers:
- A set of conversions to platform_drivers::remove_new() which gets rid
of the pointless return value.
- A new driver for the Starfive JH8100 SoC
- Support for Amlogic-T7 SoCs
- Improvement for the interrupt handling and EOI management for the
loongson interrupt controller.
- The usual fixes and improvements all over the place.
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Merge tag 'irq-core-2024-03-10' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull irq updates from Thomas Gleixner:
"Core:
- Make affinity changes take effect immediately for interrupt
threads. This reduces the impact on isolated CPUs as it pulls over
the thread right away instead of doing it after the next hardware
interrupt arrived.
- Cleanup and improvements for the interrupt chip simulator
- Deduplication of the interrupt descriptor initialization code so
the sparse and non-sparse mode share more code.
Drivers:
- A set of conversions to platform_drivers::remove_new() which gets
rid of the pointless return value.
- A new driver for the Starfive JH8100 SoC
- Support for Amlogic-T7 SoCs
- Improvement for the interrupt handling and EOI management for the
loongson interrupt controller.
- The usual fixes and improvements all over the place"
* tag 'irq-core-2024-03-10' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (33 commits)
irqchip/ts4800: Convert to platform_driver::remove_new() callback
irqchip/stm32-exti: Convert to platform_driver::remove_new() callback
irqchip/renesas-rza1: Convert to platform_driver::remove_new() callback
irqchip/renesas-irqc: Convert to platform_driver::remove_new() callback
irqchip/renesas-intc-irqpin: Convert to platform_driver::remove_new() callback
irqchip/pruss-intc: Convert to platform_driver::remove_new() callback
irqchip/mvebu-pic: Convert to platform_driver::remove_new() callback
irqchip/madera: Convert to platform_driver::remove_new() callback
irqchip/ls-scfg-msi: Convert to platform_driver::remove_new() callback
irqchip/keystone: Convert to platform_driver::remove_new() callback
irqchip/imx-irqsteer: Convert to platform_driver::remove_new() callback
irqchip/imx-intmux: Convert to platform_driver::remove_new() callback
irqchip/imgpdc: Convert to platform_driver::remove_new() callback
irqchip: Add StarFive external interrupt controller
dt-bindings: interrupt-controller: Add starfive,jh8100-intc
arm64: dts: Add gpio_intc node for Amlogic-T7 SoCs
irqchip/meson-gpio: Add support for Amlogic-T7 SoCs
dt-bindings: interrupt-controller: Add support for Amlogic-T7 SoCs
irqchip/vic: Fix a kernel-doc warning
genirq: Wake interrupt threads immediately when changing affinity
...
This commit is contained in:
Linus Torvalds
commit
02d4df78c5
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|
@ -36,6 +36,7 @@ properties:
|
|||
- amlogic,meson-a1-gpio-intc
|
||||
- amlogic,meson-s4-gpio-intc
|
||||
- amlogic,c3-gpio-intc
|
||||
- amlogic,t7-gpio-intc
|
||||
- const: amlogic,meson-gpio-intc
|
||||
|
||||
reg:
|
||||
|
|
|
|||
|
|
@ -0,0 +1,61 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/interrupt-controller/starfive,jh8100-intc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: StarFive External Interrupt Controller
|
||||
|
||||
description:
|
||||
StarFive SoC JH8100 contain a external interrupt controller. It can be used
|
||||
to handle high-level input interrupt signals. It also send the output
|
||||
interrupt signal to RISC-V PLIC.
|
||||
|
||||
maintainers:
|
||||
- Changhuang Liang <changhuang.liang@starfivetech.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: starfive,jh8100-intc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
description: APB clock for the interrupt controller
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
description: APB reset for the interrupt controller
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
interrupt-controller: true
|
||||
|
||||
"#interrupt-cells":
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- resets
|
||||
- interrupts
|
||||
- interrupt-controller
|
||||
- "#interrupt-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
interrupt-controller@12260000 {
|
||||
compatible = "starfive,jh8100-intc";
|
||||
reg = <0x12260000 0x10000>;
|
||||
clocks = <&syscrg_ne 76>;
|
||||
resets = <&syscrg_ne 13>;
|
||||
interrupts = <45>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
|
@ -20952,6 +20952,12 @@ F: Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
|
|||
F: drivers/phy/starfive/phy-jh7110-pcie.c
|
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F: drivers/phy/starfive/phy-jh7110-usb.c
|
||||
|
||||
STARFIVE JH8100 EXTERNAL INTERRUPT CONTROLLER DRIVER
|
||||
M: Changhuang Liang <changhuang.liang@starfivetech.com>
|
||||
S: Supported
|
||||
F: Documentation/devicetree/bindings/interrupt-controller/starfive,jh8100-intc.yaml
|
||||
F: drivers/irqchip/irq-starfive-jh8100-intc.c
|
||||
|
||||
STATIC BRANCH/CALL
|
||||
M: Peter Zijlstra <peterz@infradead.org>
|
||||
M: Josh Poimboeuf <jpoimboe@kernel.org>
|
||||
|
|
|
|||
|
|
@ -171,6 +171,16 @@
|
|||
};
|
||||
};
|
||||
|
||||
gpio_intc: interrupt-controller@4080 {
|
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compatible = "amlogic,t7-gpio-intc",
|
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"amlogic,meson-gpio-intc";
|
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reg = <0x0 0x4080 0x0 0x20>;
|
||||
interrupt-controller;
|
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#interrupt-cells = <2>;
|
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amlogic,channel-interrupts =
|
||||
<10 11 12 13 14 15 16 17 18 19 20 21>;
|
||||
};
|
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|
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uart_a: serial@78000 {
|
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compatible = "amlogic,t7-uart", "amlogic,meson-s4-uart";
|
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reg = <0x0 0x78000 0x0 0x18>;
|
||||
|
|
|
|||
|
|
@ -546,6 +546,17 @@ config SIFIVE_PLIC
|
|||
select IRQ_DOMAIN_HIERARCHY
|
||||
select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
|
||||
|
||||
config STARFIVE_JH8100_INTC
|
||||
bool "StarFive JH8100 External Interrupt Controller"
|
||||
depends on ARCH_STARFIVE || COMPILE_TEST
|
||||
default ARCH_STARFIVE
|
||||
select IRQ_DOMAIN_HIERARCHY
|
||||
help
|
||||
This enables support for the INTC chip found in StarFive JH8100
|
||||
SoC.
|
||||
|
||||
If you don't know what to do here, say Y.
|
||||
|
||||
config EXYNOS_IRQ_COMBINER
|
||||
bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST
|
||||
depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST
|
||||
|
|
|
|||
|
|
@ -96,6 +96,7 @@ obj-$(CONFIG_CSKY_MPINTC) += irq-csky-mpintc.o
|
|||
obj-$(CONFIG_CSKY_APB_INTC) += irq-csky-apb-intc.o
|
||||
obj-$(CONFIG_RISCV_INTC) += irq-riscv-intc.o
|
||||
obj-$(CONFIG_SIFIVE_PLIC) += irq-sifive-plic.o
|
||||
obj-$(CONFIG_STARFIVE_JH8100_INTC) += irq-starfive-jh8100-intc.o
|
||||
obj-$(CONFIG_IMX_IRQSTEER) += irq-imx-irqsteer.o
|
||||
obj-$(CONFIG_IMX_INTMUX) += irq-imx-intmux.o
|
||||
obj-$(CONFIG_IMX_MU_MSI) += irq-imx-mu-msi.o
|
||||
|
|
|
|||
|
|
@ -242,7 +242,7 @@ static int __init bcm6345_l1_init_one(struct device_node *dn,
|
|||
else if (intc->n_words != n_words)
|
||||
return -EINVAL;
|
||||
|
||||
cpu = intc->cpus[idx] = kzalloc(sizeof(*cpu) + n_words * sizeof(u32),
|
||||
cpu = intc->cpus[idx] = kzalloc(struct_size(cpu, enable_cache, n_words),
|
||||
GFP_KERNEL);
|
||||
if (!cpu)
|
||||
return -ENOMEM;
|
||||
|
|
|
|||
|
|
@ -249,7 +249,7 @@ static int __init bcm7038_l1_init_one(struct device_node *dn,
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
cpu = intc->cpus[idx] = kzalloc(sizeof(*cpu) + n_words * sizeof(u32),
|
||||
cpu = intc->cpus[idx] = kzalloc(struct_size(cpu, mask_cache, n_words),
|
||||
GFP_KERNEL);
|
||||
if (!cpu)
|
||||
return -ENOMEM;
|
||||
|
|
|
|||
|
|
@ -4436,12 +4436,12 @@ static const struct irq_domain_ops its_sgi_domain_ops = {
|
|||
|
||||
static int its_vpe_id_alloc(void)
|
||||
{
|
||||
return ida_simple_get(&its_vpeid_ida, 0, ITS_MAX_VPEID, GFP_KERNEL);
|
||||
return ida_alloc_max(&its_vpeid_ida, ITS_MAX_VPEID - 1, GFP_KERNEL);
|
||||
}
|
||||
|
||||
static void its_vpe_id_free(u16 id)
|
||||
{
|
||||
ida_simple_remove(&its_vpeid_ida, id);
|
||||
ida_free(&its_vpeid_ida, id);
|
||||
}
|
||||
|
||||
static int its_vpe_init(struct its_vpe *vpe)
|
||||
|
|
|
|||
|
|
@ -19,6 +19,7 @@
|
|||
#include <linux/percpu.h>
|
||||
#include <linux/refcount.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/iopoll.h>
|
||||
|
||||
#include <linux/irqchip.h>
|
||||
#include <linux/irqchip/arm-gic-common.h>
|
||||
|
|
@ -180,11 +181,6 @@ static enum gic_intid_range get_intid_range(struct irq_data *d)
|
|||
return __get_intid_range(d->hwirq);
|
||||
}
|
||||
|
||||
static inline unsigned int gic_irq(struct irq_data *d)
|
||||
{
|
||||
return d->hwirq;
|
||||
}
|
||||
|
||||
static inline bool gic_irq_in_rdist(struct irq_data *d)
|
||||
{
|
||||
switch (get_intid_range(d)) {
|
||||
|
|
@ -251,17 +247,13 @@ static inline void __iomem *gic_dist_base(struct irq_data *d)
|
|||
|
||||
static void gic_do_wait_for_rwp(void __iomem *base, u32 bit)
|
||||
{
|
||||
u32 count = 1000000; /* 1s! */
|
||||
u32 val;
|
||||
int ret;
|
||||
|
||||
while (readl_relaxed(base + GICD_CTLR) & bit) {
|
||||
count--;
|
||||
if (!count) {
|
||||
pr_err_ratelimited("RWP timeout, gone fishing\n");
|
||||
return;
|
||||
}
|
||||
cpu_relax();
|
||||
udelay(1);
|
||||
}
|
||||
ret = readl_relaxed_poll_timeout_atomic(base + GICD_CTLR, val, !(val & bit),
|
||||
1, USEC_PER_SEC);
|
||||
if (ret == -ETIMEDOUT)
|
||||
pr_err_ratelimited("RWP timeout, gone fishing\n");
|
||||
}
|
||||
|
||||
/* Wait for completion of a distributor change */
|
||||
|
|
@ -279,8 +271,8 @@ static void gic_redist_wait_for_rwp(void)
|
|||
static void gic_enable_redist(bool enable)
|
||||
{
|
||||
void __iomem *rbase;
|
||||
u32 count = 1000000; /* 1s! */
|
||||
u32 val;
|
||||
int ret;
|
||||
|
||||
if (gic_data.flags & FLAGS_WORKAROUND_GICR_WAKER_MSM8996)
|
||||
return;
|
||||
|
|
@ -301,16 +293,13 @@ static void gic_enable_redist(bool enable)
|
|||
return; /* No PM support in this redistributor */
|
||||
}
|
||||
|
||||
while (--count) {
|
||||
val = readl_relaxed(rbase + GICR_WAKER);
|
||||
if (enable ^ (bool)(val & GICR_WAKER_ChildrenAsleep))
|
||||
break;
|
||||
cpu_relax();
|
||||
udelay(1);
|
||||
}
|
||||
if (!count)
|
||||
ret = readl_relaxed_poll_timeout_atomic(rbase + GICR_WAKER, val,
|
||||
enable ^ (bool)(val & GICR_WAKER_ChildrenAsleep),
|
||||
1, USEC_PER_SEC);
|
||||
if (ret == -ETIMEDOUT) {
|
||||
pr_err_ratelimited("redistributor failed to %s...\n",
|
||||
enable ? "wakeup" : "sleep");
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -548,7 +537,7 @@ static int gic_irq_nmi_setup(struct irq_data *d)
|
|||
* A secondary irq_chip should be in charge of LPI request,
|
||||
* it should not be possible to get there
|
||||
*/
|
||||
if (WARN_ON(gic_irq(d) >= 8192))
|
||||
if (WARN_ON(irqd_to_hwirq(d) >= 8192))
|
||||
return -EINVAL;
|
||||
|
||||
/* desc lock should already be held */
|
||||
|
|
@ -588,7 +577,7 @@ static void gic_irq_nmi_teardown(struct irq_data *d)
|
|||
* A secondary irq_chip should be in charge of LPI request,
|
||||
* it should not be possible to get there
|
||||
*/
|
||||
if (WARN_ON(gic_irq(d) >= 8192))
|
||||
if (WARN_ON(irqd_to_hwirq(d) >= 8192))
|
||||
return;
|
||||
|
||||
/* desc lock should already be held */
|
||||
|
|
@ -626,7 +615,7 @@ static bool gic_arm64_erratum_2941627_needed(struct irq_data *d)
|
|||
|
||||
static void gic_eoi_irq(struct irq_data *d)
|
||||
{
|
||||
write_gicreg(gic_irq(d), ICC_EOIR1_EL1);
|
||||
write_gicreg(irqd_to_hwirq(d), ICC_EOIR1_EL1);
|
||||
isb();
|
||||
|
||||
if (gic_arm64_erratum_2941627_needed(d)) {
|
||||
|
|
@ -646,19 +635,19 @@ static void gic_eoimode1_eoi_irq(struct irq_data *d)
|
|||
* No need to deactivate an LPI, or an interrupt that
|
||||
* is is getting forwarded to a vcpu.
|
||||
*/
|
||||
if (gic_irq(d) >= 8192 || irqd_is_forwarded_to_vcpu(d))
|
||||
if (irqd_to_hwirq(d) >= 8192 || irqd_is_forwarded_to_vcpu(d))
|
||||
return;
|
||||
|
||||
if (!gic_arm64_erratum_2941627_needed(d))
|
||||
gic_write_dir(gic_irq(d));
|
||||
gic_write_dir(irqd_to_hwirq(d));
|
||||
else
|
||||
gic_poke_irq(d, GICD_ICACTIVER);
|
||||
}
|
||||
|
||||
static int gic_set_type(struct irq_data *d, unsigned int type)
|
||||
{
|
||||
irq_hw_number_t irq = irqd_to_hwirq(d);
|
||||
enum gic_intid_range range;
|
||||
unsigned int irq = gic_irq(d);
|
||||
void __iomem *base;
|
||||
u32 offset, index;
|
||||
int ret;
|
||||
|
|
@ -684,7 +673,7 @@ static int gic_set_type(struct irq_data *d, unsigned int type)
|
|||
ret = gic_configure_irq(index, type, base + offset, NULL);
|
||||
if (ret && (range == PPI_RANGE || range == EPPI_RANGE)) {
|
||||
/* Misconfigured PPIs are usually not fatal */
|
||||
pr_warn("GIC: PPI INTID%d is secure or misconfigured\n", irq);
|
||||
pr_warn("GIC: PPI INTID%ld is secure or misconfigured\n", irq);
|
||||
ret = 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -162,11 +162,6 @@ static inline void __iomem *gic_cpu_base(struct irq_data *d)
|
|||
return gic_data_cpu_base(gic_data);
|
||||
}
|
||||
|
||||
static inline unsigned int gic_irq(struct irq_data *d)
|
||||
{
|
||||
return d->hwirq;
|
||||
}
|
||||
|
||||
static inline bool cascading_gic_irq(struct irq_data *d)
|
||||
{
|
||||
void *data = irq_data_get_irq_handler_data(d);
|
||||
|
|
@ -183,14 +178,16 @@ static inline bool cascading_gic_irq(struct irq_data *d)
|
|||
*/
|
||||
static void gic_poke_irq(struct irq_data *d, u32 offset)
|
||||
{
|
||||
u32 mask = 1 << (gic_irq(d) % 32);
|
||||
writel_relaxed(mask, gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4);
|
||||
u32 mask = 1 << (irqd_to_hwirq(d) % 32);
|
||||
|
||||
writel_relaxed(mask, gic_dist_base(d) + offset + (irqd_to_hwirq(d) / 32) * 4);
|
||||
}
|
||||
|
||||
static int gic_peek_irq(struct irq_data *d, u32 offset)
|
||||
{
|
||||
u32 mask = 1 << (gic_irq(d) % 32);
|
||||
return !!(readl_relaxed(gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4) & mask);
|
||||
u32 mask = 1 << (irqd_to_hwirq(d) % 32);
|
||||
|
||||
return !!(readl_relaxed(gic_dist_base(d) + offset + (irqd_to_hwirq(d) / 32) * 4) & mask);
|
||||
}
|
||||
|
||||
static void gic_mask_irq(struct irq_data *d)
|
||||
|
|
@ -220,7 +217,7 @@ static void gic_unmask_irq(struct irq_data *d)
|
|||
|
||||
static void gic_eoi_irq(struct irq_data *d)
|
||||
{
|
||||
u32 hwirq = gic_irq(d);
|
||||
irq_hw_number_t hwirq = irqd_to_hwirq(d);
|
||||
|
||||
if (hwirq < 16)
|
||||
hwirq = this_cpu_read(sgi_intid);
|
||||
|
|
@ -230,7 +227,7 @@ static void gic_eoi_irq(struct irq_data *d)
|
|||
|
||||
static void gic_eoimode1_eoi_irq(struct irq_data *d)
|
||||
{
|
||||
u32 hwirq = gic_irq(d);
|
||||
irq_hw_number_t hwirq = irqd_to_hwirq(d);
|
||||
|
||||
/* Do not deactivate an IRQ forwarded to a vcpu. */
|
||||
if (irqd_is_forwarded_to_vcpu(d))
|
||||
|
|
@ -293,8 +290,8 @@ static int gic_irq_get_irqchip_state(struct irq_data *d,
|
|||
|
||||
static int gic_set_type(struct irq_data *d, unsigned int type)
|
||||
{
|
||||
irq_hw_number_t gicirq = irqd_to_hwirq(d);
|
||||
void __iomem *base = gic_dist_base(d);
|
||||
unsigned int gicirq = gic_irq(d);
|
||||
int ret;
|
||||
|
||||
/* Interrupt configuration for SGIs can't be changed */
|
||||
|
|
@ -309,7 +306,7 @@ static int gic_set_type(struct irq_data *d, unsigned int type)
|
|||
ret = gic_configure_irq(gicirq, type, base + GIC_DIST_CONFIG, NULL);
|
||||
if (ret && gicirq < 32) {
|
||||
/* Misconfigured PPIs are usually not fatal */
|
||||
pr_warn("GIC: PPI%d is secure or misconfigured\n", gicirq - 16);
|
||||
pr_warn("GIC: PPI%ld is secure or misconfigured\n", gicirq - 16);
|
||||
ret = 0;
|
||||
}
|
||||
|
||||
|
|
@ -319,7 +316,7 @@ static int gic_set_type(struct irq_data *d, unsigned int type)
|
|||
static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu)
|
||||
{
|
||||
/* Only interrupts on the primary GIC can be forwarded to a vcpu. */
|
||||
if (cascading_gic_irq(d) || gic_irq(d) < 16)
|
||||
if (cascading_gic_irq(d) || irqd_to_hwirq(d) < 16)
|
||||
return -EINVAL;
|
||||
|
||||
if (vcpu)
|
||||
|
|
@ -796,7 +793,7 @@ static void rmw_writeb(u8 bval, void __iomem *addr)
|
|||
static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
|
||||
bool force)
|
||||
{
|
||||
void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + gic_irq(d);
|
||||
void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + irqd_to_hwirq(d);
|
||||
struct gic_chip_data *gic = irq_data_get_irq_chip_data(d);
|
||||
unsigned int cpu;
|
||||
|
||||
|
|
|
|||
|
|
@ -461,12 +461,11 @@ err_generic:
|
|||
return ret;
|
||||
}
|
||||
|
||||
static int pdc_intc_remove(struct platform_device *pdev)
|
||||
static void pdc_intc_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct pdc_intc_priv *priv = platform_get_drvdata(pdev);
|
||||
|
||||
irq_domain_remove(priv->domain);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id pdc_intc_match[] = {
|
||||
|
|
@ -479,8 +478,8 @@ static struct platform_driver pdc_intc_driver = {
|
|||
.name = "pdc-intc",
|
||||
.of_match_table = pdc_intc_match,
|
||||
},
|
||||
.probe = pdc_intc_probe,
|
||||
.remove = pdc_intc_remove,
|
||||
.probe = pdc_intc_probe,
|
||||
.remove_new = pdc_intc_remove,
|
||||
};
|
||||
|
||||
static int __init pdc_intc_init(void)
|
||||
|
|
|
|||
|
|
@ -282,7 +282,7 @@ out:
|
|||
return ret;
|
||||
}
|
||||
|
||||
static int imx_intmux_remove(struct platform_device *pdev)
|
||||
static void imx_intmux_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct intmux_data *data = platform_get_drvdata(pdev);
|
||||
int i;
|
||||
|
|
@ -298,8 +298,6 @@ static int imx_intmux_remove(struct platform_device *pdev)
|
|||
}
|
||||
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
|
|
@ -354,11 +352,11 @@ static const struct of_device_id imx_intmux_id[] = {
|
|||
|
||||
static struct platform_driver imx_intmux_driver = {
|
||||
.driver = {
|
||||
.name = "imx-intmux",
|
||||
.of_match_table = imx_intmux_id,
|
||||
.pm = &imx_intmux_pm_ops,
|
||||
.name = "imx-intmux",
|
||||
.of_match_table = imx_intmux_id,
|
||||
.pm = &imx_intmux_pm_ops,
|
||||
},
|
||||
.probe = imx_intmux_probe,
|
||||
.remove = imx_intmux_remove,
|
||||
.probe = imx_intmux_probe,
|
||||
.remove_new = imx_intmux_remove,
|
||||
};
|
||||
builtin_platform_driver(imx_intmux_driver);
|
||||
|
|
|
|||
|
|
@ -231,7 +231,7 @@ out:
|
|||
return ret;
|
||||
}
|
||||
|
||||
static int imx_irqsteer_remove(struct platform_device *pdev)
|
||||
static void imx_irqsteer_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct irqsteer_data *irqsteer_data = platform_get_drvdata(pdev);
|
||||
int i;
|
||||
|
|
@ -243,8 +243,6 @@ static int imx_irqsteer_remove(struct platform_device *pdev)
|
|||
irq_domain_remove(irqsteer_data->domain);
|
||||
|
||||
clk_disable_unprepare(irqsteer_data->ipg_clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
|
|
@ -307,11 +305,11 @@ static const struct of_device_id imx_irqsteer_dt_ids[] = {
|
|||
|
||||
static struct platform_driver imx_irqsteer_driver = {
|
||||
.driver = {
|
||||
.name = "imx-irqsteer",
|
||||
.of_match_table = imx_irqsteer_dt_ids,
|
||||
.pm = &imx_irqsteer_pm_ops,
|
||||
.name = "imx-irqsteer",
|
||||
.of_match_table = imx_irqsteer_dt_ids,
|
||||
.pm = &imx_irqsteer_pm_ops,
|
||||
},
|
||||
.probe = imx_irqsteer_probe,
|
||||
.remove = imx_irqsteer_remove,
|
||||
.probe = imx_irqsteer_probe,
|
||||
.remove_new = imx_irqsteer_remove,
|
||||
};
|
||||
builtin_platform_driver(imx_irqsteer_driver);
|
||||
|
|
|
|||
|
|
@ -190,7 +190,7 @@ static int keystone_irq_probe(struct platform_device *pdev)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int keystone_irq_remove(struct platform_device *pdev)
|
||||
static void keystone_irq_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct keystone_irq_device *kirq = platform_get_drvdata(pdev);
|
||||
int hwirq;
|
||||
|
|
@ -201,7 +201,6 @@ static int keystone_irq_remove(struct platform_device *pdev)
|
|||
irq_dispose_mapping(irq_find_mapping(kirq->irqd, hwirq));
|
||||
|
||||
irq_domain_remove(kirq->irqd);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id keystone_irq_dt_ids[] = {
|
||||
|
|
@ -212,7 +211,7 @@ MODULE_DEVICE_TABLE(of, keystone_irq_dt_ids);
|
|||
|
||||
static struct platform_driver keystone_irq_device_driver = {
|
||||
.probe = keystone_irq_probe,
|
||||
.remove = keystone_irq_remove,
|
||||
.remove_new = keystone_irq_remove,
|
||||
.driver = {
|
||||
.name = "keystone_irq",
|
||||
.of_match_table = of_match_ptr(keystone_irq_dt_ids),
|
||||
|
|
|
|||
|
|
@ -198,6 +198,12 @@ static void eiointc_irq_dispatch(struct irq_desc *desc)
|
|||
|
||||
for (i = 0; i < eiointc_priv[0]->vec_count / VEC_COUNT_PER_REG; i++) {
|
||||
pending = iocsr_read64(EIOINTC_REG_ISR + (i << 3));
|
||||
|
||||
/* Skip handling if pending bitmap is zero */
|
||||
if (!pending)
|
||||
continue;
|
||||
|
||||
/* Clear the IRQs */
|
||||
iocsr_write64(pending, EIOINTC_REG_ISR + (i << 3));
|
||||
while (pending) {
|
||||
int bit = __ffs(pending);
|
||||
|
|
@ -304,23 +310,7 @@ static int eiointc_suspend(void)
|
|||
|
||||
static void eiointc_resume(void)
|
||||
{
|
||||
int i, j;
|
||||
struct irq_desc *desc;
|
||||
struct irq_data *irq_data;
|
||||
|
||||
eiointc_router_init(0);
|
||||
|
||||
for (i = 0; i < nr_pics; i++) {
|
||||
for (j = 0; j < eiointc_priv[0]->vec_count; j++) {
|
||||
desc = irq_resolve_mapping(eiointc_priv[i]->eiointc_domain, j);
|
||||
if (desc && desc->handle_irq && desc->handle_irq != handle_bad_irq) {
|
||||
raw_spin_lock(&desc->lock);
|
||||
irq_data = irq_domain_get_irq_data(eiointc_priv[i]->eiointc_domain, irq_desc_get_irq(desc));
|
||||
eiointc_set_irq_affinity(irq_data, irq_data->common->affinity, 0);
|
||||
raw_spin_unlock(&desc->lock);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static struct syscore_ops eiointc_syscore_ops = {
|
||||
|
|
|
|||
|
|
@ -398,7 +398,7 @@ static int ls_scfg_msi_probe(struct platform_device *pdev)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int ls_scfg_msi_remove(struct platform_device *pdev)
|
||||
static void ls_scfg_msi_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct ls_scfg_msi *msi_data = platform_get_drvdata(pdev);
|
||||
int i;
|
||||
|
|
@ -410,17 +410,15 @@ static int ls_scfg_msi_remove(struct platform_device *pdev)
|
|||
irq_domain_remove(msi_data->parent);
|
||||
|
||||
platform_set_drvdata(pdev, NULL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver ls_scfg_msi_driver = {
|
||||
.driver = {
|
||||
.name = "ls-scfg-msi",
|
||||
.of_match_table = ls_scfg_msi_id,
|
||||
.name = "ls-scfg-msi",
|
||||
.of_match_table = ls_scfg_msi_id,
|
||||
},
|
||||
.probe = ls_scfg_msi_probe,
|
||||
.remove = ls_scfg_msi_remove,
|
||||
.probe = ls_scfg_msi_probe,
|
||||
.remove_new = ls_scfg_msi_remove,
|
||||
};
|
||||
|
||||
module_platform_driver(ls_scfg_msi_driver);
|
||||
|
|
|
|||
|
|
@ -222,7 +222,7 @@ static int madera_irq_probe(struct platform_device *pdev)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int madera_irq_remove(struct platform_device *pdev)
|
||||
static void madera_irq_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct madera *madera = dev_get_drvdata(pdev->dev.parent);
|
||||
|
||||
|
|
@ -232,13 +232,11 @@ static int madera_irq_remove(struct platform_device *pdev)
|
|||
*/
|
||||
madera->irq_dev = NULL;
|
||||
regmap_del_irq_chip(madera->irq, madera->irq_data);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver madera_irq_driver = {
|
||||
.probe = &madera_irq_probe,
|
||||
.remove = &madera_irq_remove,
|
||||
.probe = madera_irq_probe,
|
||||
.remove_new = madera_irq_remove,
|
||||
.driver = {
|
||||
.name = "madera-irq",
|
||||
.pm = &madera_irq_pm_ops,
|
||||
|
|
|
|||
|
|
@ -154,6 +154,10 @@ static const struct meson_gpio_irq_params c3_params = {
|
|||
INIT_MESON_S4_COMMON_DATA(55)
|
||||
};
|
||||
|
||||
static const struct meson_gpio_irq_params t7_params = {
|
||||
INIT_MESON_S4_COMMON_DATA(157)
|
||||
};
|
||||
|
||||
static const struct of_device_id meson_irq_gpio_matches[] __maybe_unused = {
|
||||
{ .compatible = "amlogic,meson8-gpio-intc", .data = &meson8_params },
|
||||
{ .compatible = "amlogic,meson8b-gpio-intc", .data = &meson8b_params },
|
||||
|
|
@ -165,6 +169,7 @@ static const struct of_device_id meson_irq_gpio_matches[] __maybe_unused = {
|
|||
{ .compatible = "amlogic,meson-a1-gpio-intc", .data = &a1_params },
|
||||
{ .compatible = "amlogic,meson-s4-gpio-intc", .data = &s4_params },
|
||||
{ .compatible = "amlogic,c3-gpio-intc", .data = &c3_params },
|
||||
{ .compatible = "amlogic,t7-gpio-intc", .data = &t7_params },
|
||||
{ }
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -167,14 +167,12 @@ static int mvebu_pic_probe(struct platform_device *pdev)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int mvebu_pic_remove(struct platform_device *pdev)
|
||||
static void mvebu_pic_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct mvebu_pic *pic = platform_get_drvdata(pdev);
|
||||
|
||||
on_each_cpu(mvebu_pic_disable_percpu_irq, pic, 1);
|
||||
irq_domain_remove(pic->domain);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id mvebu_pic_of_match[] = {
|
||||
|
|
@ -184,11 +182,11 @@ static const struct of_device_id mvebu_pic_of_match[] = {
|
|||
MODULE_DEVICE_TABLE(of, mvebu_pic_of_match);
|
||||
|
||||
static struct platform_driver mvebu_pic_driver = {
|
||||
.probe = mvebu_pic_probe,
|
||||
.remove = mvebu_pic_remove,
|
||||
.probe = mvebu_pic_probe,
|
||||
.remove_new = mvebu_pic_remove,
|
||||
.driver = {
|
||||
.name = "mvebu-pic",
|
||||
.of_match_table = mvebu_pic_of_match,
|
||||
.name = "mvebu-pic",
|
||||
.of_match_table = mvebu_pic_of_match,
|
||||
},
|
||||
};
|
||||
module_platform_driver(mvebu_pic_driver);
|
||||
|
|
|
|||
|
|
@ -599,7 +599,7 @@ fail_irq:
|
|||
return ret;
|
||||
}
|
||||
|
||||
static int pruss_intc_remove(struct platform_device *pdev)
|
||||
static void pruss_intc_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct pruss_intc *intc = platform_get_drvdata(pdev);
|
||||
u8 max_system_events = intc->soc_config->num_system_events;
|
||||
|
|
@ -616,8 +616,6 @@ static int pruss_intc_remove(struct platform_device *pdev)
|
|||
irq_dispose_mapping(irq_find_mapping(intc->domain, hwirq));
|
||||
|
||||
irq_domain_remove(intc->domain);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct pruss_intc_match_data pruss_intc_data = {
|
||||
|
|
@ -645,12 +643,12 @@ MODULE_DEVICE_TABLE(of, pruss_intc_of_match);
|
|||
|
||||
static struct platform_driver pruss_intc_driver = {
|
||||
.driver = {
|
||||
.name = "pruss-intc",
|
||||
.of_match_table = pruss_intc_of_match,
|
||||
.suppress_bind_attrs = true,
|
||||
.name = "pruss-intc",
|
||||
.of_match_table = pruss_intc_of_match,
|
||||
.suppress_bind_attrs = true,
|
||||
},
|
||||
.probe = pruss_intc_probe,
|
||||
.remove = pruss_intc_remove,
|
||||
.probe = pruss_intc_probe,
|
||||
.remove_new = pruss_intc_remove,
|
||||
};
|
||||
module_platform_driver(pruss_intc_driver);
|
||||
|
||||
|
|
|
|||
|
|
@ -561,14 +561,13 @@ err0:
|
|||
return ret;
|
||||
}
|
||||
|
||||
static int intc_irqpin_remove(struct platform_device *pdev)
|
||||
static void intc_irqpin_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct intc_irqpin_priv *p = platform_get_drvdata(pdev);
|
||||
|
||||
irq_domain_remove(p->irq_domain);
|
||||
pm_runtime_put(&pdev->dev);
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __maybe_unused intc_irqpin_suspend(struct device *dev)
|
||||
|
|
@ -585,11 +584,11 @@ static SIMPLE_DEV_PM_OPS(intc_irqpin_pm_ops, intc_irqpin_suspend, NULL);
|
|||
|
||||
static struct platform_driver intc_irqpin_device_driver = {
|
||||
.probe = intc_irqpin_probe,
|
||||
.remove = intc_irqpin_remove,
|
||||
.remove_new = intc_irqpin_remove,
|
||||
.driver = {
|
||||
.name = "renesas_intc_irqpin",
|
||||
.of_match_table = intc_irqpin_dt_ids,
|
||||
.pm = &intc_irqpin_pm_ops,
|
||||
.name = "renesas_intc_irqpin",
|
||||
.of_match_table = intc_irqpin_dt_ids,
|
||||
.pm = &intc_irqpin_pm_ops,
|
||||
}
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -218,14 +218,13 @@ err_runtime_pm_disable:
|
|||
return ret;
|
||||
}
|
||||
|
||||
static int irqc_remove(struct platform_device *pdev)
|
||||
static void irqc_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct irqc_priv *p = platform_get_drvdata(pdev);
|
||||
|
||||
irq_domain_remove(p->irq_domain);
|
||||
pm_runtime_put(&pdev->dev);
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __maybe_unused irqc_suspend(struct device *dev)
|
||||
|
|
@ -248,11 +247,11 @@ MODULE_DEVICE_TABLE(of, irqc_dt_ids);
|
|||
|
||||
static struct platform_driver irqc_device_driver = {
|
||||
.probe = irqc_probe,
|
||||
.remove = irqc_remove,
|
||||
.remove_new = irqc_remove,
|
||||
.driver = {
|
||||
.name = "renesas_irqc",
|
||||
.name = "renesas_irqc",
|
||||
.of_match_table = irqc_dt_ids,
|
||||
.pm = &irqc_pm_ops,
|
||||
.pm = &irqc_pm_ops,
|
||||
}
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -244,12 +244,11 @@ out_put_node:
|
|||
return ret;
|
||||
}
|
||||
|
||||
static int rza1_irqc_remove(struct platform_device *pdev)
|
||||
static void rza1_irqc_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct rza1_irqc_priv *priv = platform_get_drvdata(pdev);
|
||||
|
||||
irq_domain_remove(priv->irq_domain);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id rza1_irqc_dt_ids[] = {
|
||||
|
|
@ -260,9 +259,9 @@ MODULE_DEVICE_TABLE(of, rza1_irqc_dt_ids);
|
|||
|
||||
static struct platform_driver rza1_irqc_device_driver = {
|
||||
.probe = rza1_irqc_probe,
|
||||
.remove = rza1_irqc_remove,
|
||||
.remove_new = rza1_irqc_remove,
|
||||
.driver = {
|
||||
.name = "renesas_rza1_irqc",
|
||||
.name = "renesas_rza1_irqc",
|
||||
.of_match_table = rza1_irqc_dt_ids,
|
||||
}
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,207 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* StarFive JH8100 External Interrupt Controller driver
|
||||
*
|
||||
* Copyright (C) 2023 StarFive Technology Co., Ltd.
|
||||
*
|
||||
* Author: Changhuang Liang <changhuang.liang@starfivetech.com>
|
||||
*/
|
||||
|
||||
#define pr_fmt(fmt) "irq-starfive-jh8100: " fmt
|
||||
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/irqchip.h>
|
||||
#include <linux/irqchip/chained_irq.h>
|
||||
#include <linux/irqdomain.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/reset.h>
|
||||
#include <linux/spinlock.h>
|
||||
|
||||
#define STARFIVE_INTC_SRC0_CLEAR 0x10
|
||||
#define STARFIVE_INTC_SRC0_MASK 0x14
|
||||
#define STARFIVE_INTC_SRC0_INT 0x1c
|
||||
|
||||
#define STARFIVE_INTC_SRC_IRQ_NUM 32
|
||||
|
||||
struct starfive_irq_chip {
|
||||
void __iomem *base;
|
||||
struct irq_domain *domain;
|
||||
raw_spinlock_t lock;
|
||||
};
|
||||
|
||||
static void starfive_intc_bit_set(struct starfive_irq_chip *irqc,
|
||||
u32 reg, u32 bit_mask)
|
||||
{
|
||||
u32 value;
|
||||
|
||||
value = ioread32(irqc->base + reg);
|
||||
value |= bit_mask;
|
||||
iowrite32(value, irqc->base + reg);
|
||||
}
|
||||
|
||||
static void starfive_intc_bit_clear(struct starfive_irq_chip *irqc,
|
||||
u32 reg, u32 bit_mask)
|
||||
{
|
||||
u32 value;
|
||||
|
||||
value = ioread32(irqc->base + reg);
|
||||
value &= ~bit_mask;
|
||||
iowrite32(value, irqc->base + reg);
|
||||
}
|
||||
|
||||
static void starfive_intc_unmask(struct irq_data *d)
|
||||
{
|
||||
struct starfive_irq_chip *irqc = irq_data_get_irq_chip_data(d);
|
||||
|
||||
raw_spin_lock(&irqc->lock);
|
||||
starfive_intc_bit_clear(irqc, STARFIVE_INTC_SRC0_MASK, BIT(d->hwirq));
|
||||
raw_spin_unlock(&irqc->lock);
|
||||
}
|
||||
|
||||
static void starfive_intc_mask(struct irq_data *d)
|
||||
{
|
||||
struct starfive_irq_chip *irqc = irq_data_get_irq_chip_data(d);
|
||||
|
||||
raw_spin_lock(&irqc->lock);
|
||||
starfive_intc_bit_set(irqc, STARFIVE_INTC_SRC0_MASK, BIT(d->hwirq));
|
||||
raw_spin_unlock(&irqc->lock);
|
||||
}
|
||||
|
||||
static struct irq_chip intc_dev = {
|
||||
.name = "StarFive JH8100 INTC",
|
||||
.irq_unmask = starfive_intc_unmask,
|
||||
.irq_mask = starfive_intc_mask,
|
||||
};
|
||||
|
||||
static int starfive_intc_map(struct irq_domain *d, unsigned int irq,
|
||||
irq_hw_number_t hwirq)
|
||||
{
|
||||
irq_domain_set_info(d, irq, hwirq, &intc_dev, d->host_data,
|
||||
handle_level_irq, NULL, NULL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct irq_domain_ops starfive_intc_domain_ops = {
|
||||
.xlate = irq_domain_xlate_onecell,
|
||||
.map = starfive_intc_map,
|
||||
};
|
||||
|
||||
static void starfive_intc_irq_handler(struct irq_desc *desc)
|
||||
{
|
||||
struct starfive_irq_chip *irqc = irq_data_get_irq_handler_data(&desc->irq_data);
|
||||
struct irq_chip *chip = irq_desc_get_chip(desc);
|
||||
unsigned long value;
|
||||
int hwirq;
|
||||
|
||||
chained_irq_enter(chip, desc);
|
||||
|
||||
value = ioread32(irqc->base + STARFIVE_INTC_SRC0_INT);
|
||||
while (value) {
|
||||
hwirq = ffs(value) - 1;
|
||||
|
||||
generic_handle_domain_irq(irqc->domain, hwirq);
|
||||
|
||||
starfive_intc_bit_set(irqc, STARFIVE_INTC_SRC0_CLEAR, BIT(hwirq));
|
||||
starfive_intc_bit_clear(irqc, STARFIVE_INTC_SRC0_CLEAR, BIT(hwirq));
|
||||
|
||||
__clear_bit(hwirq, &value);
|
||||
}
|
||||
|
||||
chained_irq_exit(chip, desc);
|
||||
}
|
||||
|
||||
static int __init starfive_intc_init(struct device_node *intc,
|
||||
struct device_node *parent)
|
||||
{
|
||||
struct starfive_irq_chip *irqc;
|
||||
struct reset_control *rst;
|
||||
struct clk *clk;
|
||||
int parent_irq;
|
||||
int ret;
|
||||
|
||||
irqc = kzalloc(sizeof(*irqc), GFP_KERNEL);
|
||||
if (!irqc)
|
||||
return -ENOMEM;
|
||||
|
||||
irqc->base = of_iomap(intc, 0);
|
||||
if (!irqc->base) {
|
||||
pr_err("Unable to map registers\n");
|
||||
ret = -ENXIO;
|
||||
goto err_free;
|
||||
}
|
||||
|
||||
rst = of_reset_control_get_exclusive(intc, NULL);
|
||||
if (IS_ERR(rst)) {
|
||||
pr_err("Unable to get reset control %pe\n", rst);
|
||||
ret = PTR_ERR(rst);
|
||||
goto err_unmap;
|
||||
}
|
||||
|
||||
clk = of_clk_get(intc, 0);
|
||||
if (IS_ERR(clk)) {
|
||||
pr_err("Unable to get clock %pe\n", clk);
|
||||
ret = PTR_ERR(clk);
|
||||
goto err_reset_put;
|
||||
}
|
||||
|
||||
ret = reset_control_deassert(rst);
|
||||
if (ret)
|
||||
goto err_clk_put;
|
||||
|
||||
ret = clk_prepare_enable(clk);
|
||||
if (ret)
|
||||
goto err_reset_assert;
|
||||
|
||||
raw_spin_lock_init(&irqc->lock);
|
||||
|
||||
irqc->domain = irq_domain_add_linear(intc, STARFIVE_INTC_SRC_IRQ_NUM,
|
||||
&starfive_intc_domain_ops, irqc);
|
||||
if (!irqc->domain) {
|
||||
pr_err("Unable to create IRQ domain\n");
|
||||
ret = -EINVAL;
|
||||
goto err_clk_disable;
|
||||
}
|
||||
|
||||
parent_irq = of_irq_get(intc, 0);
|
||||
if (parent_irq < 0) {
|
||||
pr_err("Failed to get main IRQ: %d\n", parent_irq);
|
||||
ret = parent_irq;
|
||||
goto err_remove_domain;
|
||||
}
|
||||
|
||||
irq_set_chained_handler_and_data(parent_irq, starfive_intc_irq_handler,
|
||||
irqc);
|
||||
|
||||
pr_info("Interrupt controller register, nr_irqs %d\n",
|
||||
STARFIVE_INTC_SRC_IRQ_NUM);
|
||||
|
||||
return 0;
|
||||
|
||||
err_remove_domain:
|
||||
irq_domain_remove(irqc->domain);
|
||||
err_clk_disable:
|
||||
clk_disable_unprepare(clk);
|
||||
err_reset_assert:
|
||||
reset_control_assert(rst);
|
||||
err_clk_put:
|
||||
clk_put(clk);
|
||||
err_reset_put:
|
||||
reset_control_put(rst);
|
||||
err_unmap:
|
||||
iounmap(irqc->base);
|
||||
err_free:
|
||||
kfree(irqc);
|
||||
return ret;
|
||||
}
|
||||
|
||||
IRQCHIP_PLATFORM_DRIVER_BEGIN(starfive_intc)
|
||||
IRQCHIP_MATCH("starfive,jh8100-intc", starfive_intc_init)
|
||||
IRQCHIP_PLATFORM_DRIVER_END(starfive_intc)
|
||||
|
||||
MODULE_DESCRIPTION("StarFive JH8100 External Interrupt Controller");
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_AUTHOR("Changhuang Liang <changhuang.liang@starfivetech.com>");
|
||||
|
|
@ -898,10 +898,9 @@ static void stm32_exti_remove_irq(void *data)
|
|||
irq_domain_remove(domain);
|
||||
}
|
||||
|
||||
static int stm32_exti_remove(struct platform_device *pdev)
|
||||
static void stm32_exti_remove(struct platform_device *pdev)
|
||||
{
|
||||
stm32_exti_h_syscore_deinit();
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int stm32_exti_probe(struct platform_device *pdev)
|
||||
|
|
@ -991,10 +990,10 @@ MODULE_DEVICE_TABLE(of, stm32_exti_ids);
|
|||
|
||||
static struct platform_driver stm32_exti_driver = {
|
||||
.probe = stm32_exti_probe,
|
||||
.remove = stm32_exti_remove,
|
||||
.remove_new = stm32_exti_remove,
|
||||
.driver = {
|
||||
.name = "stm32_exti",
|
||||
.of_match_table = stm32_exti_ids,
|
||||
.name = "stm32_exti",
|
||||
.of_match_table = stm32_exti_ids,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -139,13 +139,11 @@ static int ts4800_ic_probe(struct platform_device *pdev)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int ts4800_ic_remove(struct platform_device *pdev)
|
||||
static void ts4800_ic_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct ts4800_irq_data *data = platform_get_drvdata(pdev);
|
||||
|
||||
irq_domain_remove(data->domain);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id ts4800_ic_of_match[] = {
|
||||
|
|
@ -155,11 +153,11 @@ static const struct of_device_id ts4800_ic_of_match[] = {
|
|||
MODULE_DEVICE_TABLE(of, ts4800_ic_of_match);
|
||||
|
||||
static struct platform_driver ts4800_ic_driver = {
|
||||
.probe = ts4800_ic_probe,
|
||||
.remove = ts4800_ic_remove,
|
||||
.probe = ts4800_ic_probe,
|
||||
.remove_new = ts4800_ic_remove,
|
||||
.driver = {
|
||||
.name = "ts4800-irqc",
|
||||
.of_match_table = ts4800_ic_of_match,
|
||||
.name = "ts4800-irqc",
|
||||
.of_match_table = ts4800_ic_of_match,
|
||||
},
|
||||
};
|
||||
module_platform_driver(ts4800_ic_driver);
|
||||
|
|
|
|||
|
|
@ -47,9 +47,8 @@
|
|||
|
||||
/**
|
||||
* struct vic_device - VIC PM device
|
||||
* @parent_irq: The parent IRQ number of the VIC if cascaded, or 0.
|
||||
* @irq: The IRQ number for the base of the VIC.
|
||||
* @base: The register base for the VIC.
|
||||
* @irq: The IRQ number for the base of the VIC.
|
||||
* @valid_sources: A bitmask of valid interrupts
|
||||
* @resume_sources: A bitmask of interrupts for resume.
|
||||
* @resume_irqs: The IRQs enabled for resume.
|
||||
|
|
|
|||
|
|
@ -6,6 +6,7 @@
|
|||
|
||||
#include <linux/align.h>
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/cleanup.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/find.h>
|
||||
#include <linux/limits.h>
|
||||
|
|
@ -127,6 +128,8 @@ unsigned long *bitmap_alloc_node(unsigned int nbits, gfp_t flags, int node);
|
|||
unsigned long *bitmap_zalloc_node(unsigned int nbits, gfp_t flags, int node);
|
||||
void bitmap_free(const unsigned long *bitmap);
|
||||
|
||||
DEFINE_FREE(bitmap, unsigned long *, if (_T) bitmap_free(_T))
|
||||
|
||||
/* Managed variants of the above. */
|
||||
unsigned long *devm_bitmap_alloc(struct device *dev,
|
||||
unsigned int nbits, gfp_t flags);
|
||||
|
|
|
|||
|
|
@ -179,7 +179,7 @@ struct irq_common_data {
|
|||
struct irq_data {
|
||||
u32 mask;
|
||||
unsigned int irq;
|
||||
unsigned long hwirq;
|
||||
irq_hw_number_t hwirq;
|
||||
struct irq_common_data *common;
|
||||
struct irq_chip *chip;
|
||||
struct irq_domain *domain;
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
*/
|
||||
|
||||
struct irq_desc;
|
||||
struct irq_data;
|
||||
|
||||
typedef void (*irq_flow_handler_t)(struct irq_desc *desc);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -4,10 +4,11 @@
|
|||
* Copyright (C) 2020 Bartosz Golaszewski <bgolaszewski@baylibre.com>
|
||||
*/
|
||||
|
||||
#include <linux/cleanup.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/irq_sim.h>
|
||||
#include <linux/irq_work.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/slab.h>
|
||||
|
||||
struct irq_sim_work_ctx {
|
||||
|
|
@ -19,7 +20,6 @@ struct irq_sim_work_ctx {
|
|||
};
|
||||
|
||||
struct irq_sim_irq_ctx {
|
||||
int irqnum;
|
||||
bool enabled;
|
||||
struct irq_sim_work_ctx *work_ctx;
|
||||
};
|
||||
|
|
@ -164,33 +164,27 @@ static const struct irq_domain_ops irq_sim_domain_ops = {
|
|||
struct irq_domain *irq_domain_create_sim(struct fwnode_handle *fwnode,
|
||||
unsigned int num_irqs)
|
||||
{
|
||||
struct irq_sim_work_ctx *work_ctx;
|
||||
struct irq_sim_work_ctx *work_ctx __free(kfree) =
|
||||
kmalloc(sizeof(*work_ctx), GFP_KERNEL);
|
||||
|
||||
work_ctx = kmalloc(sizeof(*work_ctx), GFP_KERNEL);
|
||||
if (!work_ctx)
|
||||
goto err_out;
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
work_ctx->pending = bitmap_zalloc(num_irqs, GFP_KERNEL);
|
||||
if (!work_ctx->pending)
|
||||
goto err_free_work_ctx;
|
||||
unsigned long *pending __free(bitmap) = bitmap_zalloc(num_irqs, GFP_KERNEL);
|
||||
if (!pending)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
work_ctx->domain = irq_domain_create_linear(fwnode, num_irqs,
|
||||
&irq_sim_domain_ops,
|
||||
work_ctx);
|
||||
if (!work_ctx->domain)
|
||||
goto err_free_bitmap;
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
work_ctx->irq_count = num_irqs;
|
||||
work_ctx->work = IRQ_WORK_INIT_HARD(irq_sim_handle_irq);
|
||||
work_ctx->pending = no_free_ptr(pending);
|
||||
|
||||
return work_ctx->domain;
|
||||
|
||||
err_free_bitmap:
|
||||
bitmap_free(work_ctx->pending);
|
||||
err_free_work_ctx:
|
||||
kfree(work_ctx);
|
||||
err_out:
|
||||
return ERR_PTR(-ENOMEM);
|
||||
return no_free_ptr(work_ctx)->domain;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(irq_domain_create_sim);
|
||||
|
||||
|
|
|
|||
|
|
@ -92,11 +92,23 @@ static void desc_smp_init(struct irq_desc *desc, int node,
|
|||
#endif
|
||||
}
|
||||
|
||||
static void free_masks(struct irq_desc *desc)
|
||||
{
|
||||
#ifdef CONFIG_GENERIC_PENDING_IRQ
|
||||
free_cpumask_var(desc->pending_mask);
|
||||
#endif
|
||||
free_cpumask_var(desc->irq_common_data.affinity);
|
||||
#ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK
|
||||
free_cpumask_var(desc->irq_common_data.effective_affinity);
|
||||
#endif
|
||||
}
|
||||
|
||||
#else
|
||||
static inline int
|
||||
alloc_masks(struct irq_desc *desc, int node) { return 0; }
|
||||
static inline void
|
||||
desc_smp_init(struct irq_desc *desc, int node, const struct cpumask *affinity) { }
|
||||
static inline void free_masks(struct irq_desc *desc) { }
|
||||
#endif
|
||||
|
||||
static void desc_set_defaults(unsigned int irq, struct irq_desc *desc, int node,
|
||||
|
|
@ -165,6 +177,39 @@ static void delete_irq_desc(unsigned int irq)
|
|||
mas_erase(&mas);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SPARSE_IRQ
|
||||
static const struct kobj_type irq_kobj_type;
|
||||
#endif
|
||||
|
||||
static int init_desc(struct irq_desc *desc, int irq, int node,
|
||||
unsigned int flags,
|
||||
const struct cpumask *affinity,
|
||||
struct module *owner)
|
||||
{
|
||||
desc->kstat_irqs = alloc_percpu(unsigned int);
|
||||
if (!desc->kstat_irqs)
|
||||
return -ENOMEM;
|
||||
|
||||
if (alloc_masks(desc, node)) {
|
||||
free_percpu(desc->kstat_irqs);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
raw_spin_lock_init(&desc->lock);
|
||||
lockdep_set_class(&desc->lock, &irq_desc_lock_class);
|
||||
mutex_init(&desc->request_mutex);
|
||||
init_waitqueue_head(&desc->wait_for_threads);
|
||||
desc_set_defaults(irq, desc, node, affinity, owner);
|
||||
irqd_set(&desc->irq_data, flags);
|
||||
irq_resend_init(desc);
|
||||
#ifdef CONFIG_SPARSE_IRQ
|
||||
kobject_init(&desc->kobj, &irq_kobj_type);
|
||||
init_rcu_head(&desc->rcu);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SPARSE_IRQ
|
||||
|
||||
static void irq_kobj_release(struct kobject *kobj);
|
||||
|
|
@ -384,21 +429,6 @@ struct irq_desc *irq_to_desc(unsigned int irq)
|
|||
EXPORT_SYMBOL_GPL(irq_to_desc);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
static void free_masks(struct irq_desc *desc)
|
||||
{
|
||||
#ifdef CONFIG_GENERIC_PENDING_IRQ
|
||||
free_cpumask_var(desc->pending_mask);
|
||||
#endif
|
||||
free_cpumask_var(desc->irq_common_data.affinity);
|
||||
#ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK
|
||||
free_cpumask_var(desc->irq_common_data.effective_affinity);
|
||||
#endif
|
||||
}
|
||||
#else
|
||||
static inline void free_masks(struct irq_desc *desc) { }
|
||||
#endif
|
||||
|
||||
void irq_lock_sparse(void)
|
||||
{
|
||||
mutex_lock(&sparse_irq_lock);
|
||||
|
|
@ -414,36 +444,19 @@ static struct irq_desc *alloc_desc(int irq, int node, unsigned int flags,
|
|||
struct module *owner)
|
||||
{
|
||||
struct irq_desc *desc;
|
||||
int ret;
|
||||
|
||||
desc = kzalloc_node(sizeof(*desc), GFP_KERNEL, node);
|
||||
if (!desc)
|
||||
return NULL;
|
||||
/* allocate based on nr_cpu_ids */
|
||||
desc->kstat_irqs = alloc_percpu(unsigned int);
|
||||
if (!desc->kstat_irqs)
|
||||
goto err_desc;
|
||||
|
||||
if (alloc_masks(desc, node))
|
||||
goto err_kstat;
|
||||
|
||||
raw_spin_lock_init(&desc->lock);
|
||||
lockdep_set_class(&desc->lock, &irq_desc_lock_class);
|
||||
mutex_init(&desc->request_mutex);
|
||||
init_rcu_head(&desc->rcu);
|
||||
init_waitqueue_head(&desc->wait_for_threads);
|
||||
|
||||
desc_set_defaults(irq, desc, node, affinity, owner);
|
||||
irqd_set(&desc->irq_data, flags);
|
||||
kobject_init(&desc->kobj, &irq_kobj_type);
|
||||
irq_resend_init(desc);
|
||||
ret = init_desc(desc, irq, node, flags, affinity, owner);
|
||||
if (unlikely(ret)) {
|
||||
kfree(desc);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
return desc;
|
||||
|
||||
err_kstat:
|
||||
free_percpu(desc->kstat_irqs);
|
||||
err_desc:
|
||||
kfree(desc);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static void irq_kobj_release(struct kobject *kobj)
|
||||
|
|
@ -583,26 +596,29 @@ struct irq_desc irq_desc[NR_IRQS] __cacheline_aligned_in_smp = {
|
|||
int __init early_irq_init(void)
|
||||
{
|
||||
int count, i, node = first_online_node;
|
||||
struct irq_desc *desc;
|
||||
int ret;
|
||||
|
||||
init_irq_default_affinity();
|
||||
|
||||
printk(KERN_INFO "NR_IRQS: %d\n", NR_IRQS);
|
||||
|
||||
desc = irq_desc;
|
||||
count = ARRAY_SIZE(irq_desc);
|
||||
|
||||
for (i = 0; i < count; i++) {
|
||||
desc[i].kstat_irqs = alloc_percpu(unsigned int);
|
||||
alloc_masks(&desc[i], node);
|
||||
raw_spin_lock_init(&desc[i].lock);
|
||||
lockdep_set_class(&desc[i].lock, &irq_desc_lock_class);
|
||||
mutex_init(&desc[i].request_mutex);
|
||||
init_waitqueue_head(&desc[i].wait_for_threads);
|
||||
desc_set_defaults(i, &desc[i], node, NULL, NULL);
|
||||
irq_resend_init(&desc[i]);
|
||||
ret = init_desc(irq_desc + i, i, node, 0, NULL, NULL);
|
||||
if (unlikely(ret))
|
||||
goto __free_desc_res;
|
||||
}
|
||||
|
||||
return arch_early_irq_init();
|
||||
|
||||
__free_desc_res:
|
||||
while (--i >= 0) {
|
||||
free_masks(irq_desc + i);
|
||||
free_percpu(irq_desc[i].kstat_irqs);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
struct irq_desc *irq_to_desc(unsigned int irq)
|
||||
|
|
|
|||
|
|
@ -192,10 +192,14 @@ void irq_set_thread_affinity(struct irq_desc *desc)
|
|||
struct irqaction *action;
|
||||
|
||||
for_each_action_of_desc(desc, action) {
|
||||
if (action->thread)
|
||||
if (action->thread) {
|
||||
set_bit(IRQTF_AFFINITY, &action->thread_flags);
|
||||
if (action->secondary && action->secondary->thread)
|
||||
wake_up_process(action->thread);
|
||||
}
|
||||
if (action->secondary && action->secondary->thread) {
|
||||
set_bit(IRQTF_AFFINITY, &action->secondary->thread_flags);
|
||||
wake_up_process(action->secondary->thread);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1049,10 +1053,57 @@ static irqreturn_t irq_forced_secondary_handler(int irq, void *dev_id)
|
|||
return IRQ_NONE;
|
||||
}
|
||||
|
||||
static int irq_wait_for_interrupt(struct irqaction *action)
|
||||
#ifdef CONFIG_SMP
|
||||
/*
|
||||
* Check whether we need to change the affinity of the interrupt thread.
|
||||
*/
|
||||
static void irq_thread_check_affinity(struct irq_desc *desc, struct irqaction *action)
|
||||
{
|
||||
cpumask_var_t mask;
|
||||
bool valid = false;
|
||||
|
||||
if (!test_and_clear_bit(IRQTF_AFFINITY, &action->thread_flags))
|
||||
return;
|
||||
|
||||
__set_current_state(TASK_RUNNING);
|
||||
|
||||
/*
|
||||
* In case we are out of memory we set IRQTF_AFFINITY again and
|
||||
* try again next time
|
||||
*/
|
||||
if (!alloc_cpumask_var(&mask, GFP_KERNEL)) {
|
||||
set_bit(IRQTF_AFFINITY, &action->thread_flags);
|
||||
return;
|
||||
}
|
||||
|
||||
raw_spin_lock_irq(&desc->lock);
|
||||
/*
|
||||
* This code is triggered unconditionally. Check the affinity
|
||||
* mask pointer. For CPU_MASK_OFFSTACK=n this is optimized out.
|
||||
*/
|
||||
if (cpumask_available(desc->irq_common_data.affinity)) {
|
||||
const struct cpumask *m;
|
||||
|
||||
m = irq_data_get_effective_affinity_mask(&desc->irq_data);
|
||||
cpumask_copy(mask, m);
|
||||
valid = true;
|
||||
}
|
||||
raw_spin_unlock_irq(&desc->lock);
|
||||
|
||||
if (valid)
|
||||
set_cpus_allowed_ptr(current, mask);
|
||||
free_cpumask_var(mask);
|
||||
}
|
||||
#else
|
||||
static inline void irq_thread_check_affinity(struct irq_desc *desc, struct irqaction *action) { }
|
||||
#endif
|
||||
|
||||
static int irq_wait_for_interrupt(struct irq_desc *desc,
|
||||
struct irqaction *action)
|
||||
{
|
||||
for (;;) {
|
||||
set_current_state(TASK_INTERRUPTIBLE);
|
||||
irq_thread_check_affinity(desc, action);
|
||||
|
||||
if (kthread_should_stop()) {
|
||||
/* may need to run one last time */
|
||||
|
|
@ -1129,52 +1180,6 @@ out_unlock:
|
|||
chip_bus_sync_unlock(desc);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
/*
|
||||
* Check whether we need to change the affinity of the interrupt thread.
|
||||
*/
|
||||
static void
|
||||
irq_thread_check_affinity(struct irq_desc *desc, struct irqaction *action)
|
||||
{
|
||||
cpumask_var_t mask;
|
||||
bool valid = true;
|
||||
|
||||
if (!test_and_clear_bit(IRQTF_AFFINITY, &action->thread_flags))
|
||||
return;
|
||||
|
||||
/*
|
||||
* In case we are out of memory we set IRQTF_AFFINITY again and
|
||||
* try again next time
|
||||
*/
|
||||
if (!alloc_cpumask_var(&mask, GFP_KERNEL)) {
|
||||
set_bit(IRQTF_AFFINITY, &action->thread_flags);
|
||||
return;
|
||||
}
|
||||
|
||||
raw_spin_lock_irq(&desc->lock);
|
||||
/*
|
||||
* This code is triggered unconditionally. Check the affinity
|
||||
* mask pointer. For CPU_MASK_OFFSTACK=n this is optimized out.
|
||||
*/
|
||||
if (cpumask_available(desc->irq_common_data.affinity)) {
|
||||
const struct cpumask *m;
|
||||
|
||||
m = irq_data_get_effective_affinity_mask(&desc->irq_data);
|
||||
cpumask_copy(mask, m);
|
||||
} else {
|
||||
valid = false;
|
||||
}
|
||||
raw_spin_unlock_irq(&desc->lock);
|
||||
|
||||
if (valid)
|
||||
set_cpus_allowed_ptr(current, mask);
|
||||
free_cpumask_var(mask);
|
||||
}
|
||||
#else
|
||||
static inline void
|
||||
irq_thread_check_affinity(struct irq_desc *desc, struct irqaction *action) { }
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Interrupts which are not explicitly requested as threaded
|
||||
* interrupts rely on the implicit bh/preempt disable of the hard irq
|
||||
|
|
@ -1312,13 +1317,9 @@ static int irq_thread(void *data)
|
|||
init_task_work(&on_exit_work, irq_thread_dtor);
|
||||
task_work_add(current, &on_exit_work, TWA_NONE);
|
||||
|
||||
irq_thread_check_affinity(desc, action);
|
||||
|
||||
while (!irq_wait_for_interrupt(action)) {
|
||||
while (!irq_wait_for_interrupt(desc, action)) {
|
||||
irqreturn_t action_ret;
|
||||
|
||||
irq_thread_check_affinity(desc, action);
|
||||
|
||||
action_ret = handler_fn(desc, action);
|
||||
if (action_ret == IRQ_WAKE_THREAD)
|
||||
irq_wake_secondary(desc, action);
|
||||
|
|
|
|||
Loading…
Reference in New Issue