2023-08-23 04:45:40 -04:00
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/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
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2022-09-06 10:38:21 -04:00
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#ifndef __DT_BINDINGS_POWER_RK3588_POWER_H__
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#define __DT_BINDINGS_POWER_RK3588_POWER_H__
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/* VD_LITDSU */
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#define RK3588_PD_CPU_0 0
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#define RK3588_PD_CPU_1 1
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#define RK3588_PD_CPU_2 2
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#define RK3588_PD_CPU_3 3
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/* VD_BIGCORE0 */
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#define RK3588_PD_CPU_4 4
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#define RK3588_PD_CPU_5 5
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/* VD_BIGCORE1 */
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#define RK3588_PD_CPU_6 6
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#define RK3588_PD_CPU_7 7
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/* VD_NPU */
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#define RK3588_PD_NPU 8
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#define RK3588_PD_NPUTOP 9
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#define RK3588_PD_NPU1 10
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#define RK3588_PD_NPU2 11
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/* VD_GPU */
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#define RK3588_PD_GPU 12
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/* VD_VCODEC */
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#define RK3588_PD_VCODEC 13
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#define RK3588_PD_RKVDEC0 14
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#define RK3588_PD_RKVDEC1 15
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#define RK3588_PD_VENC0 16
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#define RK3588_PD_VENC1 17
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/* VD_DD01 */
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#define RK3588_PD_DDR01 18
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/* VD_DD23 */
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#define RK3588_PD_DDR23 19
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/* VD_LOGIC */
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#define RK3588_PD_CENTER 20
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#define RK3588_PD_VDPU 21
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#define RK3588_PD_RGA30 22
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#define RK3588_PD_AV1 23
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#define RK3588_PD_VOP 24
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#define RK3588_PD_VO0 25
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#define RK3588_PD_VO1 26
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#define RK3588_PD_VI 27
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#define RK3588_PD_ISP1 28
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#define RK3588_PD_FEC 29
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#define RK3588_PD_RGA31 30
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#define RK3588_PD_USB 31
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#define RK3588_PD_PHP 32
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#define RK3588_PD_GMAC 33
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#define RK3588_PD_PCIE 34
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#define RK3588_PD_NVM 35
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#define RK3588_PD_NVM0 36
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#define RK3588_PD_SDIO 37
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#define RK3588_PD_AUDIO 38
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#define RK3588_PD_SECURE 39
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#define RK3588_PD_SDMMC 40
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#define RK3588_PD_CRYPTO 41
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#define RK3588_PD_BUS 42
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/* VD_PMU */
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#define RK3588_PD_PMU1 43
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#endif
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