License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default
license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license
identifiers to apply.
- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:
SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became
the concluded license(s).
- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.
In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.
Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 10:07:57 -04:00
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// SPDX-License-Identifier: GPL-2.0
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2017-01-22 07:18:44 -05:00
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/*
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2017-03-12 19:28:16 -04:00
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* Faraday Technolog FTGPIO010 gpiochip and interrupt routines
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2017-01-22 07:18:44 -05:00
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* Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
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*
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* Based on arch/arm/mach-gemini/gpio.c:
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* Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
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*
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* Based on plat-mxc/gpio.c:
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* MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
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* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
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*/
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#include <linux/gpio/driver.h>
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#include <linux/io.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/bitops.h>
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2018-08-27 16:15:40 -04:00
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#include <linux/clk.h>
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2017-01-22 07:18:44 -05:00
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/* GPIO registers definition */
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#define GPIO_DATA_OUT 0x00
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#define GPIO_DATA_IN 0x04
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#define GPIO_DIR 0x08
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2018-02-12 16:40:23 -05:00
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#define GPIO_BYPASS_IN 0x0C
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2017-01-22 07:18:44 -05:00
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#define GPIO_DATA_SET 0x10
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#define GPIO_DATA_CLR 0x14
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#define GPIO_PULL_EN 0x18
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#define GPIO_PULL_TYPE 0x1C
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#define GPIO_INT_EN 0x20
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2018-02-12 16:40:23 -05:00
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#define GPIO_INT_STAT_RAW 0x24
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#define GPIO_INT_STAT_MASKED 0x28
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2017-01-22 07:18:44 -05:00
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#define GPIO_INT_MASK 0x2C
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#define GPIO_INT_CLR 0x30
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#define GPIO_INT_TYPE 0x34
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#define GPIO_INT_BOTH_EDGE 0x38
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#define GPIO_INT_LEVEL 0x3C
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#define GPIO_DEBOUNCE_EN 0x40
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#define GPIO_DEBOUNCE_PRESCALE 0x44
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/**
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2017-03-12 19:28:16 -04:00
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* struct ftgpio_gpio - Gemini GPIO state container
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2017-01-22 07:18:44 -05:00
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* @dev: containing device for this instance
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* @gc: gpiochip for this instance
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2018-08-27 16:15:40 -04:00
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* @base: remapped I/O-memory base
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* @clk: silicon clock
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2017-01-22 07:18:44 -05:00
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*/
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2017-03-12 19:28:16 -04:00
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struct ftgpio_gpio {
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2017-01-22 07:18:44 -05:00
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struct device *dev;
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struct gpio_chip gc;
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void __iomem *base;
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2018-08-27 16:15:40 -04:00
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struct clk *clk;
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2017-01-22 07:18:44 -05:00
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};
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2017-03-12 19:28:16 -04:00
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static void ftgpio_gpio_ack_irq(struct irq_data *d)
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2017-01-22 07:18:44 -05:00
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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2017-03-12 19:28:16 -04:00
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struct ftgpio_gpio *g = gpiochip_get_data(gc);
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2017-01-22 07:18:44 -05:00
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writel(BIT(irqd_to_hwirq(d)), g->base + GPIO_INT_CLR);
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}
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2017-03-12 19:28:16 -04:00
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static void ftgpio_gpio_mask_irq(struct irq_data *d)
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2017-01-22 07:18:44 -05:00
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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2017-03-12 19:28:16 -04:00
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struct ftgpio_gpio *g = gpiochip_get_data(gc);
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2017-01-22 07:18:44 -05:00
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u32 val;
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val = readl(g->base + GPIO_INT_EN);
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val &= ~BIT(irqd_to_hwirq(d));
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writel(val, g->base + GPIO_INT_EN);
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2022-09-15 16:32:54 -04:00
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gpiochip_disable_irq(gc, irqd_to_hwirq(d));
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2017-01-22 07:18:44 -05:00
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}
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2017-03-12 19:28:16 -04:00
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static void ftgpio_gpio_unmask_irq(struct irq_data *d)
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2017-01-22 07:18:44 -05:00
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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2017-03-12 19:28:16 -04:00
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struct ftgpio_gpio *g = gpiochip_get_data(gc);
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2017-01-22 07:18:44 -05:00
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u32 val;
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2022-09-15 16:32:54 -04:00
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gpiochip_enable_irq(gc, irqd_to_hwirq(d));
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2017-01-22 07:18:44 -05:00
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val = readl(g->base + GPIO_INT_EN);
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val |= BIT(irqd_to_hwirq(d));
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writel(val, g->base + GPIO_INT_EN);
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}
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2017-03-12 19:28:16 -04:00
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static int ftgpio_gpio_set_irq_type(struct irq_data *d, unsigned int type)
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2017-01-22 07:18:44 -05:00
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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2017-03-12 19:28:16 -04:00
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struct ftgpio_gpio *g = gpiochip_get_data(gc);
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2017-01-22 07:18:44 -05:00
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u32 mask = BIT(irqd_to_hwirq(d));
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u32 reg_both, reg_level, reg_type;
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reg_type = readl(g->base + GPIO_INT_TYPE);
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reg_level = readl(g->base + GPIO_INT_LEVEL);
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reg_both = readl(g->base + GPIO_INT_BOTH_EDGE);
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switch (type) {
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case IRQ_TYPE_EDGE_BOTH:
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irq_set_handler_locked(d, handle_edge_irq);
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reg_type &= ~mask;
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reg_both |= mask;
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break;
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case IRQ_TYPE_EDGE_RISING:
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irq_set_handler_locked(d, handle_edge_irq);
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reg_type &= ~mask;
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reg_both &= ~mask;
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reg_level &= ~mask;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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irq_set_handler_locked(d, handle_edge_irq);
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reg_type &= ~mask;
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reg_both &= ~mask;
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reg_level |= mask;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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irq_set_handler_locked(d, handle_level_irq);
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reg_type |= mask;
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reg_level &= ~mask;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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irq_set_handler_locked(d, handle_level_irq);
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reg_type |= mask;
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reg_level |= mask;
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break;
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default:
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irq_set_handler_locked(d, handle_bad_irq);
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return -EINVAL;
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}
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writel(reg_type, g->base + GPIO_INT_TYPE);
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writel(reg_level, g->base + GPIO_INT_LEVEL);
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writel(reg_both, g->base + GPIO_INT_BOTH_EDGE);
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2017-03-12 19:28:16 -04:00
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ftgpio_gpio_ack_irq(d);
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2017-01-22 07:18:44 -05:00
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return 0;
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}
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2017-03-12 19:28:16 -04:00
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static void ftgpio_gpio_irq_handler(struct irq_desc *desc)
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2017-01-22 07:18:44 -05:00
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{
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struct gpio_chip *gc = irq_desc_get_handler_data(desc);
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2017-03-12 19:28:16 -04:00
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struct ftgpio_gpio *g = gpiochip_get_data(gc);
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2017-01-22 07:18:44 -05:00
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struct irq_chip *irqchip = irq_desc_get_chip(desc);
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int offset;
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unsigned long stat;
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chained_irq_enter(irqchip, desc);
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2018-02-12 16:40:23 -05:00
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stat = readl(g->base + GPIO_INT_STAT_RAW);
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2017-01-22 07:18:44 -05:00
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if (stat)
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for_each_set_bit(offset, &stat, gc->ngpio)
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2021-05-04 12:42:18 -04:00
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generic_handle_domain_irq(gc->irq.domain, offset);
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2017-01-22 07:18:44 -05:00
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chained_irq_exit(irqchip, desc);
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}
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2018-08-27 16:15:51 -04:00
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static int ftgpio_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
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unsigned long config)
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{
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enum pin_config_param param = pinconf_to_config_param(config);
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u32 arg = pinconf_to_config_argument(config);
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struct ftgpio_gpio *g = gpiochip_get_data(gc);
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unsigned long pclk_freq;
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u32 deb_div;
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u32 val;
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if (param != PIN_CONFIG_INPUT_DEBOUNCE)
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return -ENOTSUPP;
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/*
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* Debounce only works if interrupts are enabled. The manual
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* states that if PCLK is 66 MHz, and this is set to 0x7D0, then
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* PCLK is divided down to 33 kHz for the debounce timer. 0x7D0 is
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* 2000 decimal, so what they mean is simply that the PCLK is
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* divided by this value.
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*
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* As we get a debounce setting in microseconds, we calculate the
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* desired period time and see if we can get a suitable debounce
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* time.
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*/
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pclk_freq = clk_get_rate(g->clk);
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deb_div = DIV_ROUND_CLOSEST(pclk_freq, arg);
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/* This register is only 24 bits wide */
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if (deb_div > (1 << 24))
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return -ENOTSUPP;
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dev_dbg(g->dev, "prescale divisor: %08x, resulting frequency %lu Hz\n",
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deb_div, (pclk_freq/deb_div));
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val = readl(g->base + GPIO_DEBOUNCE_PRESCALE);
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if (val == deb_div) {
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/*
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* The debounce timer happens to already be set to the
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2020-04-24 11:41:02 -04:00
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* desirable value, what a coincidence! We can just enable
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2018-08-27 16:15:51 -04:00
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* debounce on this GPIO line and return. This happens more
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* often than you think, for example when all GPIO keys
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* on a system are requesting the same debounce interval.
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*/
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val = readl(g->base + GPIO_DEBOUNCE_EN);
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val |= BIT(offset);
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writel(val, g->base + GPIO_DEBOUNCE_EN);
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return 0;
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}
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val = readl(g->base + GPIO_DEBOUNCE_EN);
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if (val) {
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/*
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* Oh no! Someone is already using the debounce with
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* another setting than what we need. Bummer.
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*/
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return -ENOTSUPP;
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}
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/* First come, first serve */
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writel(deb_div, g->base + GPIO_DEBOUNCE_PRESCALE);
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/* Enable debounce */
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val |= BIT(offset);
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writel(val, g->base + GPIO_DEBOUNCE_EN);
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return 0;
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}
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2022-09-15 16:32:54 -04:00
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static const struct irq_chip ftgpio_irq_chip = {
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.name = "FTGPIO010",
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.irq_ack = ftgpio_gpio_ack_irq,
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.irq_mask = ftgpio_gpio_mask_irq,
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.irq_unmask = ftgpio_gpio_unmask_irq,
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.irq_set_type = ftgpio_gpio_set_irq_type,
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.flags = IRQCHIP_IMMUTABLE,
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GPIOCHIP_IRQ_RESOURCE_HELPERS,
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};
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2017-03-12 19:28:16 -04:00
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static int ftgpio_gpio_probe(struct platform_device *pdev)
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2017-01-22 07:18:44 -05:00
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{
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struct device *dev = &pdev->dev;
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2017-03-12 19:28:16 -04:00
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struct ftgpio_gpio *g;
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2019-06-13 10:11:42 -04:00
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struct gpio_irq_chip *girq;
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2017-01-22 07:18:44 -05:00
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int irq;
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int ret;
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g = devm_kzalloc(dev, sizeof(*g), GFP_KERNEL);
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if (!g)
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return -ENOMEM;
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g->dev = dev;
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2019-03-11 14:54:50 -04:00
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g->base = devm_platform_ioremap_resource(pdev, 0);
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2017-01-22 07:18:44 -05:00
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if (IS_ERR(g->base))
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return PTR_ERR(g->base);
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irq = platform_get_irq(pdev, 0);
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2023-08-02 23:39:37 -04:00
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if (irq < 0)
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return irq;
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2017-01-22 07:18:44 -05:00
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2018-08-27 16:15:40 -04:00
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g->clk = devm_clk_get(dev, NULL);
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if (!IS_ERR(g->clk)) {
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ret = clk_prepare_enable(g->clk);
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if (ret)
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return ret;
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} else if (PTR_ERR(g->clk) == -EPROBE_DEFER) {
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/*
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* Percolate deferrals, for anything else,
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* just live without the clocking.
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*/
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return PTR_ERR(g->clk);
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}
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2017-01-22 07:18:44 -05:00
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ret = bgpio_init(&g->gc, dev, 4,
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g->base + GPIO_DATA_IN,
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g->base + GPIO_DATA_SET,
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g->base + GPIO_DATA_CLR,
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g->base + GPIO_DIR,
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NULL,
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0);
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if (ret) {
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dev_err(dev, "unable to init generic GPIO\n");
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2018-08-27 16:15:40 -04:00
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goto dis_clk;
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2017-01-22 07:18:44 -05:00
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}
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2022-10-24 04:08:28 -04:00
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g->gc.label = dev_name(dev);
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2017-01-22 07:18:44 -05:00
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g->gc.base = -1;
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g->gc.parent = dev;
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g->gc.owner = THIS_MODULE;
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/* ngpio is set by bgpio_init() */
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2018-08-27 16:15:51 -04:00
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/* We need a silicon clock to do debounce */
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if (!IS_ERR(g->clk))
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g->gc.set_config = ftgpio_gpio_set_config;
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2019-06-13 10:11:42 -04:00
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girq = &g->gc.irq;
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2022-09-15 16:32:54 -04:00
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gpio_irq_chip_set_chip(girq, &ftgpio_irq_chip);
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2019-06-13 10:11:42 -04:00
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girq->parent_handler = ftgpio_gpio_irq_handler;
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girq->num_parents = 1;
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girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents),
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GFP_KERNEL);
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2019-08-22 16:45:38 -04:00
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if (!girq->parents) {
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ret = -ENOMEM;
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goto dis_clk;
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}
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2019-06-13 10:11:42 -04:00
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girq->default_type = IRQ_TYPE_NONE;
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girq->handler = handle_bad_irq;
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girq->parents[0] = irq;
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2017-01-22 07:18:44 -05:00
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/* Disable, unmask and clear all interrupts */
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writel(0x0, g->base + GPIO_INT_EN);
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writel(0x0, g->base + GPIO_INT_MASK);
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writel(~0x0, g->base + GPIO_INT_CLR);
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2018-08-27 16:15:51 -04:00
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/* Clear any use of debounce */
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writel(0x0, g->base + GPIO_DEBOUNCE_EN);
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2019-08-19 04:27:04 -04:00
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ret = devm_gpiochip_add_data(dev, &g->gc, g);
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if (ret)
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goto dis_clk;
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2018-08-27 16:15:40 -04:00
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platform_set_drvdata(pdev, g);
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2017-03-12 19:28:16 -04:00
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dev_info(dev, "FTGPIO010 @%p registered\n", g->base);
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2017-01-22 07:18:44 -05:00
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return 0;
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2018-08-27 16:15:40 -04:00
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dis_clk:
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2022-05-16 04:50:00 -04:00
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clk_disable_unprepare(g->clk);
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2018-08-27 16:15:40 -04:00
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return ret;
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}
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2023-09-28 03:06:49 -04:00
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static void ftgpio_gpio_remove(struct platform_device *pdev)
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2018-08-27 16:15:40 -04:00
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{
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struct ftgpio_gpio *g = platform_get_drvdata(pdev);
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2022-05-16 04:50:00 -04:00
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clk_disable_unprepare(g->clk);
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2017-01-22 07:18:44 -05:00
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}
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2017-03-12 19:28:16 -04:00
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static const struct of_device_id ftgpio_gpio_of_match[] = {
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2017-01-22 07:18:44 -05:00
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{
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.compatible = "cortina,gemini-gpio",
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},
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2017-03-12 19:28:16 -04:00
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{
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.compatible = "moxa,moxart-gpio",
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},
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{
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.compatible = "faraday,ftgpio010",
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},
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2017-01-22 07:18:44 -05:00
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{},
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};
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2017-03-12 19:28:16 -04:00
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static struct platform_driver ftgpio_gpio_driver = {
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2017-01-22 07:18:44 -05:00
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.driver = {
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2017-03-12 19:28:16 -04:00
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.name = "ftgpio010-gpio",
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2023-03-11 06:13:00 -05:00
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.of_match_table = ftgpio_gpio_of_match,
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2017-01-22 07:18:44 -05:00
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},
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2018-08-27 16:15:40 -04:00
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.probe = ftgpio_gpio_probe,
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2023-09-28 03:06:49 -04:00
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.remove_new = ftgpio_gpio_remove,
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2017-01-22 07:18:44 -05:00
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};
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2017-03-12 19:28:16 -04:00
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builtin_platform_driver(ftgpio_gpio_driver);
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