70 lines
2.8 KiB
Plaintext
70 lines
2.8 KiB
Plaintext
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spi_lm70llp : LM70-LLP parport-to-SPI adapter
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==============================================
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Supported board/chip:
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* National Semiconductor LM70 LLP evaluation board
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Datasheet: http://www.national.com/pf/LM/LM70.html
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Author:
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Kaiwan N Billimoria <kaiwan@designergraphix.com>
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Description
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-----------
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This driver provides glue code connecting a National Semiconductor LM70 LLP
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temperature sensor evaluation board to the kernel's SPI core subsystem.
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In effect, this driver turns the parallel port interface on the eval board
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into a SPI bus with a single device, which will be driven by the generic
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LM70 driver (drivers/hwmon/lm70.c).
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The hardware interfacing on the LM70 LLP eval board is as follows:
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Parallel LM70 LLP
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Port Direction JP2 Header
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----------- --------- ----------------
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D0 2 - -
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D1 3 --> V+ 5
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D2 4 --> V+ 5
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D3 5 --> V+ 5
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D4 6 --> V+ 5
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D5 7 --> nCS 8
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D6 8 --> SCLK 3
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D7 9 --> SI/O 5
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GND 25 - GND 7
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Select 13 <-- SI/O 1
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----------- --------- ----------------
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Note that since the LM70 uses a "3-wire" variant of SPI, the SI/SO pin
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is connected to both pin D7 (as Master Out) and Select (as Master In)
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using an arrangment that lets either the parport or the LM70 pull the
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pin low. This can't be shared with true SPI devices, but other 3-wire
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devices might share the same SI/SO pin.
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The bitbanger routine in this driver (lm70_txrx) is called back from
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the bound "hwmon/lm70" protocol driver through its sysfs hook, using a
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spi_write_then_read() call. It performs Mode 0 (SPI/Microwire) bitbanging.
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The lm70 driver then inteprets the resulting digital temperature value
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and exports it through sysfs.
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A "gotcha": National Semiconductor's LM70 LLP eval board circuit schematic
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shows that the SI/O line from the LM70 chip is connected to the base of a
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transistor Q1 (and also a pullup, and a zener diode to D7); while the
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collector is tied to VCC.
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Interpreting this circuit, when the LM70 SI/O line is High (or tristate
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and not grounded by the host via D7), the transistor conducts and switches
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the collector to zero, which is reflected on pin 13 of the DB25 parport
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connector. When SI/O is Low (driven by the LM70 or the host) on the other
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hand, the transistor is cut off and the voltage tied to it's collector is
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reflected on pin 13 as a High level.
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So: the getmiso inline routine in this driver takes this fact into account,
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inverting the value read at pin 13.
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Thanks to
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---------
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o David Brownell for mentoring the SPI-side driver development.
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o Dr.Craig Hollabaugh for the (early) "manual" bitbanging driver version.
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o Nadir Billimoria for help interpreting the circuit schematic.
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