474 lines
15 KiB
C
474 lines
15 KiB
C
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#ifndef __bif_dma_defs_h
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#define __bif_dma_defs_h
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/*
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* This file is autogenerated from
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* file: ../../inst/bif/rtl/bif_dma_regs.r
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* id: bif_dma_regs.r,v 1.6 2005/02/04 13:28:31 perz Exp
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* last modfied: Mon Apr 11 16:06:33 2005
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*
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* by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_dma_defs.h ../../inst/bif/rtl/bif_dma_regs.r
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* id: $Id: bif_dma_defs.h,v 1.2 2005/04/24 18:30:58 starvik Exp $
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* Any changes here will be lost.
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*
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* -*- buffer-read-only: t -*-
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*/
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/* Main access macros */
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#ifndef REG_RD
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#define REG_RD( scope, inst, reg ) \
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REG_READ( reg_##scope##_##reg, \
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(inst) + REG_RD_ADDR_##scope##_##reg )
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#endif
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#ifndef REG_WR
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#define REG_WR( scope, inst, reg, val ) \
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REG_WRITE( reg_##scope##_##reg, \
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(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
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#endif
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#ifndef REG_RD_VECT
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#define REG_RD_VECT( scope, inst, reg, index ) \
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REG_READ( reg_##scope##_##reg, \
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(inst) + REG_RD_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg )
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#endif
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#ifndef REG_WR_VECT
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#define REG_WR_VECT( scope, inst, reg, index, val ) \
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REG_WRITE( reg_##scope##_##reg, \
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(inst) + REG_WR_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg, (val) )
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#endif
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#ifndef REG_RD_INT
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#define REG_RD_INT( scope, inst, reg ) \
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REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
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#endif
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#ifndef REG_WR_INT
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#define REG_WR_INT( scope, inst, reg, val ) \
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REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
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#endif
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#ifndef REG_RD_INT_VECT
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#define REG_RD_INT_VECT( scope, inst, reg, index ) \
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REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg )
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#endif
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#ifndef REG_WR_INT_VECT
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#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
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REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg, (val) )
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#endif
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#ifndef REG_TYPE_CONV
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#define REG_TYPE_CONV( type, orgtype, val ) \
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( { union { orgtype o; type n; } r; r.o = val; r.n; } )
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#endif
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#ifndef reg_page_size
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#define reg_page_size 8192
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#endif
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#ifndef REG_ADDR
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#define REG_ADDR( scope, inst, reg ) \
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( (inst) + REG_RD_ADDR_##scope##_##reg )
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#endif
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#ifndef REG_ADDR_VECT
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#define REG_ADDR_VECT( scope, inst, reg, index ) \
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( (inst) + REG_RD_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg )
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#endif
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/* C-code for register scope bif_dma */
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/* Register rw_ch0_ctrl, scope bif_dma, type rw */
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typedef struct {
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unsigned int bw : 2;
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unsigned int burst_len : 1;
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unsigned int cont : 1;
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unsigned int end_pad : 1;
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unsigned int cnt : 1;
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unsigned int dreq_pin : 3;
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unsigned int dreq_mode : 2;
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unsigned int tc_in_pin : 3;
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unsigned int tc_in_mode : 2;
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unsigned int bus_mode : 2;
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unsigned int rate_en : 1;
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unsigned int wr_all : 1;
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unsigned int dummy1 : 12;
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} reg_bif_dma_rw_ch0_ctrl;
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#define REG_RD_ADDR_bif_dma_rw_ch0_ctrl 0
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#define REG_WR_ADDR_bif_dma_rw_ch0_ctrl 0
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/* Register rw_ch0_addr, scope bif_dma, type rw */
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typedef struct {
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unsigned int addr : 32;
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} reg_bif_dma_rw_ch0_addr;
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#define REG_RD_ADDR_bif_dma_rw_ch0_addr 4
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#define REG_WR_ADDR_bif_dma_rw_ch0_addr 4
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/* Register rw_ch0_start, scope bif_dma, type rw */
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typedef struct {
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unsigned int run : 1;
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unsigned int dummy1 : 31;
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} reg_bif_dma_rw_ch0_start;
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#define REG_RD_ADDR_bif_dma_rw_ch0_start 8
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#define REG_WR_ADDR_bif_dma_rw_ch0_start 8
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/* Register rw_ch0_cnt, scope bif_dma, type rw */
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typedef struct {
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unsigned int start_cnt : 16;
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unsigned int dummy1 : 16;
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} reg_bif_dma_rw_ch0_cnt;
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#define REG_RD_ADDR_bif_dma_rw_ch0_cnt 12
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#define REG_WR_ADDR_bif_dma_rw_ch0_cnt 12
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/* Register r_ch0_stat, scope bif_dma, type r */
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typedef struct {
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unsigned int cnt : 16;
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unsigned int dummy1 : 15;
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unsigned int run : 1;
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} reg_bif_dma_r_ch0_stat;
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#define REG_RD_ADDR_bif_dma_r_ch0_stat 16
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/* Register rw_ch1_ctrl, scope bif_dma, type rw */
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typedef struct {
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unsigned int bw : 2;
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unsigned int burst_len : 1;
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unsigned int cont : 1;
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unsigned int end_discard : 1;
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unsigned int cnt : 1;
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unsigned int dreq_pin : 3;
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unsigned int dreq_mode : 2;
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unsigned int tc_in_pin : 3;
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unsigned int tc_in_mode : 2;
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unsigned int bus_mode : 2;
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unsigned int rate_en : 1;
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unsigned int dummy1 : 13;
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} reg_bif_dma_rw_ch1_ctrl;
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#define REG_RD_ADDR_bif_dma_rw_ch1_ctrl 32
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#define REG_WR_ADDR_bif_dma_rw_ch1_ctrl 32
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/* Register rw_ch1_addr, scope bif_dma, type rw */
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typedef struct {
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unsigned int addr : 32;
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} reg_bif_dma_rw_ch1_addr;
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#define REG_RD_ADDR_bif_dma_rw_ch1_addr 36
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#define REG_WR_ADDR_bif_dma_rw_ch1_addr 36
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/* Register rw_ch1_start, scope bif_dma, type rw */
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typedef struct {
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unsigned int run : 1;
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unsigned int dummy1 : 31;
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} reg_bif_dma_rw_ch1_start;
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#define REG_RD_ADDR_bif_dma_rw_ch1_start 40
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#define REG_WR_ADDR_bif_dma_rw_ch1_start 40
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/* Register rw_ch1_cnt, scope bif_dma, type rw */
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typedef struct {
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unsigned int start_cnt : 16;
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unsigned int dummy1 : 16;
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} reg_bif_dma_rw_ch1_cnt;
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#define REG_RD_ADDR_bif_dma_rw_ch1_cnt 44
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#define REG_WR_ADDR_bif_dma_rw_ch1_cnt 44
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/* Register r_ch1_stat, scope bif_dma, type r */
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typedef struct {
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unsigned int cnt : 16;
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unsigned int dummy1 : 15;
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unsigned int run : 1;
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} reg_bif_dma_r_ch1_stat;
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#define REG_RD_ADDR_bif_dma_r_ch1_stat 48
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/* Register rw_ch2_ctrl, scope bif_dma, type rw */
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typedef struct {
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unsigned int bw : 2;
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unsigned int burst_len : 1;
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unsigned int cont : 1;
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unsigned int end_pad : 1;
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unsigned int cnt : 1;
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unsigned int dreq_pin : 3;
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unsigned int dreq_mode : 2;
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unsigned int tc_in_pin : 3;
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unsigned int tc_in_mode : 2;
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unsigned int bus_mode : 2;
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unsigned int rate_en : 1;
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unsigned int wr_all : 1;
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unsigned int dummy1 : 12;
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} reg_bif_dma_rw_ch2_ctrl;
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#define REG_RD_ADDR_bif_dma_rw_ch2_ctrl 64
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#define REG_WR_ADDR_bif_dma_rw_ch2_ctrl 64
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/* Register rw_ch2_addr, scope bif_dma, type rw */
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typedef struct {
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unsigned int addr : 32;
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} reg_bif_dma_rw_ch2_addr;
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#define REG_RD_ADDR_bif_dma_rw_ch2_addr 68
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#define REG_WR_ADDR_bif_dma_rw_ch2_addr 68
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/* Register rw_ch2_start, scope bif_dma, type rw */
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typedef struct {
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unsigned int run : 1;
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unsigned int dummy1 : 31;
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} reg_bif_dma_rw_ch2_start;
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#define REG_RD_ADDR_bif_dma_rw_ch2_start 72
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#define REG_WR_ADDR_bif_dma_rw_ch2_start 72
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/* Register rw_ch2_cnt, scope bif_dma, type rw */
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typedef struct {
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unsigned int start_cnt : 16;
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unsigned int dummy1 : 16;
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} reg_bif_dma_rw_ch2_cnt;
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#define REG_RD_ADDR_bif_dma_rw_ch2_cnt 76
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#define REG_WR_ADDR_bif_dma_rw_ch2_cnt 76
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/* Register r_ch2_stat, scope bif_dma, type r */
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typedef struct {
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unsigned int cnt : 16;
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unsigned int dummy1 : 15;
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unsigned int run : 1;
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} reg_bif_dma_r_ch2_stat;
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#define REG_RD_ADDR_bif_dma_r_ch2_stat 80
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/* Register rw_ch3_ctrl, scope bif_dma, type rw */
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typedef struct {
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unsigned int bw : 2;
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unsigned int burst_len : 1;
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unsigned int cont : 1;
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unsigned int end_discard : 1;
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unsigned int cnt : 1;
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unsigned int dreq_pin : 3;
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unsigned int dreq_mode : 2;
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unsigned int tc_in_pin : 3;
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unsigned int tc_in_mode : 2;
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unsigned int bus_mode : 2;
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unsigned int rate_en : 1;
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unsigned int dummy1 : 13;
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} reg_bif_dma_rw_ch3_ctrl;
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#define REG_RD_ADDR_bif_dma_rw_ch3_ctrl 96
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#define REG_WR_ADDR_bif_dma_rw_ch3_ctrl 96
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/* Register rw_ch3_addr, scope bif_dma, type rw */
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typedef struct {
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unsigned int addr : 32;
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} reg_bif_dma_rw_ch3_addr;
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#define REG_RD_ADDR_bif_dma_rw_ch3_addr 100
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#define REG_WR_ADDR_bif_dma_rw_ch3_addr 100
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/* Register rw_ch3_start, scope bif_dma, type rw */
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typedef struct {
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unsigned int run : 1;
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unsigned int dummy1 : 31;
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} reg_bif_dma_rw_ch3_start;
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#define REG_RD_ADDR_bif_dma_rw_ch3_start 104
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#define REG_WR_ADDR_bif_dma_rw_ch3_start 104
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/* Register rw_ch3_cnt, scope bif_dma, type rw */
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typedef struct {
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unsigned int start_cnt : 16;
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unsigned int dummy1 : 16;
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} reg_bif_dma_rw_ch3_cnt;
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#define REG_RD_ADDR_bif_dma_rw_ch3_cnt 108
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#define REG_WR_ADDR_bif_dma_rw_ch3_cnt 108
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/* Register r_ch3_stat, scope bif_dma, type r */
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typedef struct {
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unsigned int cnt : 16;
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unsigned int dummy1 : 15;
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unsigned int run : 1;
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} reg_bif_dma_r_ch3_stat;
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#define REG_RD_ADDR_bif_dma_r_ch3_stat 112
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/* Register rw_intr_mask, scope bif_dma, type rw */
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typedef struct {
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unsigned int ext_dma0 : 1;
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unsigned int ext_dma1 : 1;
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unsigned int ext_dma2 : 1;
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unsigned int ext_dma3 : 1;
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unsigned int dummy1 : 28;
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} reg_bif_dma_rw_intr_mask;
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#define REG_RD_ADDR_bif_dma_rw_intr_mask 128
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#define REG_WR_ADDR_bif_dma_rw_intr_mask 128
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/* Register rw_ack_intr, scope bif_dma, type rw */
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typedef struct {
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unsigned int ext_dma0 : 1;
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unsigned int ext_dma1 : 1;
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unsigned int ext_dma2 : 1;
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unsigned int ext_dma3 : 1;
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unsigned int dummy1 : 28;
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} reg_bif_dma_rw_ack_intr;
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#define REG_RD_ADDR_bif_dma_rw_ack_intr 132
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#define REG_WR_ADDR_bif_dma_rw_ack_intr 132
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/* Register r_intr, scope bif_dma, type r */
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typedef struct {
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unsigned int ext_dma0 : 1;
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unsigned int ext_dma1 : 1;
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unsigned int ext_dma2 : 1;
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unsigned int ext_dma3 : 1;
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unsigned int dummy1 : 28;
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} reg_bif_dma_r_intr;
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#define REG_RD_ADDR_bif_dma_r_intr 136
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/* Register r_masked_intr, scope bif_dma, type r */
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typedef struct {
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unsigned int ext_dma0 : 1;
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unsigned int ext_dma1 : 1;
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unsigned int ext_dma2 : 1;
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unsigned int ext_dma3 : 1;
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unsigned int dummy1 : 28;
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} reg_bif_dma_r_masked_intr;
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#define REG_RD_ADDR_bif_dma_r_masked_intr 140
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/* Register rw_pin0_cfg, scope bif_dma, type rw */
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typedef struct {
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unsigned int master_ch : 2;
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unsigned int master_mode : 3;
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unsigned int slave_ch : 2;
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unsigned int slave_mode : 3;
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unsigned int dummy1 : 22;
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} reg_bif_dma_rw_pin0_cfg;
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#define REG_RD_ADDR_bif_dma_rw_pin0_cfg 160
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#define REG_WR_ADDR_bif_dma_rw_pin0_cfg 160
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/* Register rw_pin1_cfg, scope bif_dma, type rw */
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typedef struct {
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unsigned int master_ch : 2;
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unsigned int master_mode : 3;
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unsigned int slave_ch : 2;
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unsigned int slave_mode : 3;
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unsigned int dummy1 : 22;
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} reg_bif_dma_rw_pin1_cfg;
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#define REG_RD_ADDR_bif_dma_rw_pin1_cfg 164
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#define REG_WR_ADDR_bif_dma_rw_pin1_cfg 164
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/* Register rw_pin2_cfg, scope bif_dma, type rw */
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typedef struct {
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unsigned int master_ch : 2;
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unsigned int master_mode : 3;
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unsigned int slave_ch : 2;
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unsigned int slave_mode : 3;
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unsigned int dummy1 : 22;
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} reg_bif_dma_rw_pin2_cfg;
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#define REG_RD_ADDR_bif_dma_rw_pin2_cfg 168
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#define REG_WR_ADDR_bif_dma_rw_pin2_cfg 168
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/* Register rw_pin3_cfg, scope bif_dma, type rw */
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typedef struct {
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unsigned int master_ch : 2;
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unsigned int master_mode : 3;
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unsigned int slave_ch : 2;
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unsigned int slave_mode : 3;
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unsigned int dummy1 : 22;
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} reg_bif_dma_rw_pin3_cfg;
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#define REG_RD_ADDR_bif_dma_rw_pin3_cfg 172
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#define REG_WR_ADDR_bif_dma_rw_pin3_cfg 172
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/* Register rw_pin4_cfg, scope bif_dma, type rw */
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typedef struct {
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unsigned int master_ch : 2;
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unsigned int master_mode : 3;
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unsigned int slave_ch : 2;
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unsigned int slave_mode : 3;
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unsigned int dummy1 : 22;
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} reg_bif_dma_rw_pin4_cfg;
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#define REG_RD_ADDR_bif_dma_rw_pin4_cfg 176
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#define REG_WR_ADDR_bif_dma_rw_pin4_cfg 176
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/* Register rw_pin5_cfg, scope bif_dma, type rw */
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typedef struct {
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unsigned int master_ch : 2;
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unsigned int master_mode : 3;
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unsigned int slave_ch : 2;
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||
|
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unsigned int slave_mode : 3;
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unsigned int dummy1 : 22;
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||
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} reg_bif_dma_rw_pin5_cfg;
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#define REG_RD_ADDR_bif_dma_rw_pin5_cfg 180
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#define REG_WR_ADDR_bif_dma_rw_pin5_cfg 180
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|
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/* Register rw_pin6_cfg, scope bif_dma, type rw */
|
||
|
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typedef struct {
|
||
|
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unsigned int master_ch : 2;
|
||
|
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unsigned int master_mode : 3;
|
||
|
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unsigned int slave_ch : 2;
|
||
|
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unsigned int slave_mode : 3;
|
||
|
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unsigned int dummy1 : 22;
|
||
|
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} reg_bif_dma_rw_pin6_cfg;
|
||
|
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#define REG_RD_ADDR_bif_dma_rw_pin6_cfg 184
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|
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#define REG_WR_ADDR_bif_dma_rw_pin6_cfg 184
|
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|
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|
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|
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/* Register rw_pin7_cfg, scope bif_dma, type rw */
|
||
|
|
typedef struct {
|
||
|
|
unsigned int master_ch : 2;
|
||
|
|
unsigned int master_mode : 3;
|
||
|
|
unsigned int slave_ch : 2;
|
||
|
|
unsigned int slave_mode : 3;
|
||
|
|
unsigned int dummy1 : 22;
|
||
|
|
} reg_bif_dma_rw_pin7_cfg;
|
||
|
|
#define REG_RD_ADDR_bif_dma_rw_pin7_cfg 188
|
||
|
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#define REG_WR_ADDR_bif_dma_rw_pin7_cfg 188
|
||
|
|
|
||
|
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/* Register r_pin_stat, scope bif_dma, type r */
|
||
|
|
typedef struct {
|
||
|
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unsigned int pin0 : 1;
|
||
|
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unsigned int pin1 : 1;
|
||
|
|
unsigned int pin2 : 1;
|
||
|
|
unsigned int pin3 : 1;
|
||
|
|
unsigned int pin4 : 1;
|
||
|
|
unsigned int pin5 : 1;
|
||
|
|
unsigned int pin6 : 1;
|
||
|
|
unsigned int pin7 : 1;
|
||
|
|
unsigned int dummy1 : 24;
|
||
|
|
} reg_bif_dma_r_pin_stat;
|
||
|
|
#define REG_RD_ADDR_bif_dma_r_pin_stat 192
|
||
|
|
|
||
|
|
|
||
|
|
/* Constants */
|
||
|
|
enum {
|
||
|
|
regk_bif_dma_as_master = 0x00000001,
|
||
|
|
regk_bif_dma_as_slave = 0x00000001,
|
||
|
|
regk_bif_dma_burst1 = 0x00000000,
|
||
|
|
regk_bif_dma_burst8 = 0x00000001,
|
||
|
|
regk_bif_dma_bw16 = 0x00000001,
|
||
|
|
regk_bif_dma_bw32 = 0x00000002,
|
||
|
|
regk_bif_dma_bw8 = 0x00000000,
|
||
|
|
regk_bif_dma_dack = 0x00000006,
|
||
|
|
regk_bif_dma_dack_inv = 0x00000007,
|
||
|
|
regk_bif_dma_force = 0x00000001,
|
||
|
|
regk_bif_dma_hi = 0x00000003,
|
||
|
|
regk_bif_dma_inv = 0x00000003,
|
||
|
|
regk_bif_dma_lo = 0x00000002,
|
||
|
|
regk_bif_dma_master = 0x00000001,
|
||
|
|
regk_bif_dma_no = 0x00000000,
|
||
|
|
regk_bif_dma_norm = 0x00000002,
|
||
|
|
regk_bif_dma_off = 0x00000000,
|
||
|
|
regk_bif_dma_rw_ch0_ctrl_default = 0x00000000,
|
||
|
|
regk_bif_dma_rw_ch0_start_default = 0x00000000,
|
||
|
|
regk_bif_dma_rw_ch1_ctrl_default = 0x00000000,
|
||
|
|
regk_bif_dma_rw_ch1_start_default = 0x00000000,
|
||
|
|
regk_bif_dma_rw_ch2_ctrl_default = 0x00000000,
|
||
|
|
regk_bif_dma_rw_ch2_start_default = 0x00000000,
|
||
|
|
regk_bif_dma_rw_ch3_ctrl_default = 0x00000000,
|
||
|
|
regk_bif_dma_rw_ch3_start_default = 0x00000000,
|
||
|
|
regk_bif_dma_rw_intr_mask_default = 0x00000000,
|
||
|
|
regk_bif_dma_rw_pin0_cfg_default = 0x00000000,
|
||
|
|
regk_bif_dma_rw_pin1_cfg_default = 0x00000000,
|
||
|
|
regk_bif_dma_rw_pin2_cfg_default = 0x00000000,
|
||
|
|
regk_bif_dma_rw_pin3_cfg_default = 0x00000000,
|
||
|
|
regk_bif_dma_rw_pin4_cfg_default = 0x00000000,
|
||
|
|
regk_bif_dma_rw_pin5_cfg_default = 0x00000000,
|
||
|
|
regk_bif_dma_rw_pin6_cfg_default = 0x00000000,
|
||
|
|
regk_bif_dma_rw_pin7_cfg_default = 0x00000000,
|
||
|
|
regk_bif_dma_slave = 0x00000002,
|
||
|
|
regk_bif_dma_sreq = 0x00000006,
|
||
|
|
regk_bif_dma_sreq_inv = 0x00000007,
|
||
|
|
regk_bif_dma_tc = 0x00000004,
|
||
|
|
regk_bif_dma_tc_inv = 0x00000005,
|
||
|
|
regk_bif_dma_yes = 0x00000001
|
||
|
|
};
|
||
|
|
#endif /* __bif_dma_defs_h */
|