2019-06-04 04:11:33 -04:00
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// SPDX-License-Identifier: GPL-2.0-only
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2016-01-04 14:36:38 -05:00
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/*
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* Ralink MT7621/MT7628 built-in hardware watchdog timer
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*
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2016-12-20 13:56:59 -05:00
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* Copyright (C) 2014 John Crispin <john@phrozen.org>
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2016-01-04 14:36:38 -05:00
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*
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* This driver was based on: drivers/watchdog/rt2880_wdt.c
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*/
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#include <linux/clk.h>
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#include <linux/reset.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/watchdog.h>
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#include <linux/moduleparam.h>
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#include <linux/platform_device.h>
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#include <linux/mod_devicetable.h>
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#include <linux/mfd/syscon.h>
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#include <linux/regmap.h>
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#define SYSC_RSTSTAT 0x38
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#define WDT_RST_CAUSE BIT(1)
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#define RALINK_WDT_TIMEOUT 30
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#define TIMER_REG_TMRSTAT 0x00
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#define TIMER_REG_TMR1LOAD 0x24
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#define TIMER_REG_TMR1CTL 0x20
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#define TMR1CTL_ENABLE BIT(7)
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#define TMR1CTL_RESTART BIT(9)
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#define TMR1CTL_PRESCALE_SHIFT 16
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2023-02-14 05:39:35 -05:00
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struct mt7621_wdt_data {
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void __iomem *base;
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struct reset_control *rst;
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struct regmap *sysc;
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struct watchdog_device wdt;
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};
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2016-01-04 14:36:38 -05:00
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static bool nowayout = WATCHDOG_NOWAYOUT;
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module_param(nowayout, bool, 0);
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MODULE_PARM_DESC(nowayout,
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"Watchdog cannot be stopped once started (default="
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__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
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static inline void rt_wdt_w32(void __iomem *base, unsigned int reg, u32 val)
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{
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iowrite32(val, base + reg);
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}
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static inline u32 rt_wdt_r32(void __iomem *base, unsigned int reg)
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{
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return ioread32(base + reg);
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}
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static int mt7621_wdt_ping(struct watchdog_device *w)
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{
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struct mt7621_wdt_data *drvdata = watchdog_get_drvdata(w);
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rt_wdt_w32(drvdata->base, TIMER_REG_TMRSTAT, TMR1CTL_RESTART);
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return 0;
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}
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static int mt7621_wdt_set_timeout(struct watchdog_device *w, unsigned int t)
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{
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struct mt7621_wdt_data *drvdata = watchdog_get_drvdata(w);
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w->timeout = t;
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rt_wdt_w32(drvdata->base, TIMER_REG_TMR1LOAD, t * 1000);
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mt7621_wdt_ping(w);
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return 0;
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}
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static int mt7621_wdt_start(struct watchdog_device *w)
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{
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struct mt7621_wdt_data *drvdata = watchdog_get_drvdata(w);
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u32 t;
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/* set the prescaler to 1ms == 1000us */
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rt_wdt_w32(drvdata->base, TIMER_REG_TMR1CTL, 1000 << TMR1CTL_PRESCALE_SHIFT);
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mt7621_wdt_set_timeout(w, w->timeout);
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t = rt_wdt_r32(drvdata->base, TIMER_REG_TMR1CTL);
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t |= TMR1CTL_ENABLE;
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rt_wdt_w32(drvdata->base, TIMER_REG_TMR1CTL, t);
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return 0;
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}
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static int mt7621_wdt_stop(struct watchdog_device *w)
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{
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struct mt7621_wdt_data *drvdata = watchdog_get_drvdata(w);
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u32 t;
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mt7621_wdt_ping(w);
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t = rt_wdt_r32(drvdata->base, TIMER_REG_TMR1CTL);
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t &= ~TMR1CTL_ENABLE;
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rt_wdt_w32(drvdata->base, TIMER_REG_TMR1CTL, t);
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return 0;
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}
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static int mt7621_wdt_bootcause(struct mt7621_wdt_data *d)
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{
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u32 val;
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regmap_read(d->sysc, SYSC_RSTSTAT, &val);
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if (val & WDT_RST_CAUSE)
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return WDIOF_CARDRESET;
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return 0;
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}
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2018-01-12 04:44:53 -05:00
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static int mt7621_wdt_is_running(struct watchdog_device *w)
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{
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struct mt7621_wdt_data *drvdata = watchdog_get_drvdata(w);
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return !!(rt_wdt_r32(drvdata->base, TIMER_REG_TMR1CTL) & TMR1CTL_ENABLE);
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}
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2017-08-03 17:21:31 -04:00
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static const struct watchdog_info mt7621_wdt_info = {
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.identity = "Mediatek Watchdog",
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.options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
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};
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2017-01-28 02:41:17 -05:00
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static const struct watchdog_ops mt7621_wdt_ops = {
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.owner = THIS_MODULE,
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.start = mt7621_wdt_start,
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.stop = mt7621_wdt_stop,
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.ping = mt7621_wdt_ping,
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.set_timeout = mt7621_wdt_set_timeout,
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};
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static int mt7621_wdt_probe(struct platform_device *pdev)
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{
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struct device_node *np = pdev->dev.of_node;
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struct device *dev = &pdev->dev;
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struct watchdog_device *mt7621_wdt;
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struct mt7621_wdt_data *drvdata;
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int err;
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drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
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if (!drvdata)
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return -ENOMEM;
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drvdata->sysc = syscon_regmap_lookup_by_phandle(np, "mediatek,sysctl");
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if (IS_ERR(drvdata->sysc)) {
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drvdata->sysc = syscon_regmap_lookup_by_compatible("mediatek,mt7621-sysc");
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if (IS_ERR(drvdata->sysc))
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return PTR_ERR(drvdata->sysc);
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}
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drvdata->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(drvdata->base))
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return PTR_ERR(drvdata->base);
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drvdata->rst = devm_reset_control_get_exclusive(dev, NULL);
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if (!IS_ERR(drvdata->rst))
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reset_control_deassert(drvdata->rst);
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mt7621_wdt = &drvdata->wdt;
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mt7621_wdt->info = &mt7621_wdt_info;
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mt7621_wdt->ops = &mt7621_wdt_ops;
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mt7621_wdt->min_timeout = 1;
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mt7621_wdt->max_timeout = 0xfffful / 1000;
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mt7621_wdt->parent = dev;
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mt7621_wdt->bootstatus = mt7621_wdt_bootcause(drvdata);
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watchdog_init_timeout(mt7621_wdt, mt7621_wdt->max_timeout, dev);
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watchdog_set_nowayout(mt7621_wdt, nowayout);
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watchdog_set_drvdata(mt7621_wdt, drvdata);
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if (mt7621_wdt_is_running(mt7621_wdt)) {
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2018-01-12 04:44:53 -05:00
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/*
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* Make sure to apply timeout from watchdog core, taking
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* the prescaler of this driver here into account (the
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* boot loader might be using a different prescaler).
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*
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* To avoid spurious resets because of different scaling,
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* we first disable the watchdog, set the new prescaler
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* and timeout, and then re-enable the watchdog.
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*/
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mt7621_wdt_stop(mt7621_wdt);
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mt7621_wdt_start(mt7621_wdt);
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set_bit(WDOG_HW_RUNNING, &mt7621_wdt->status);
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}
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err = devm_watchdog_register_device(dev, &drvdata->wdt);
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if (err)
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return err;
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platform_set_drvdata(pdev, drvdata);
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return 0;
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}
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static void mt7621_wdt_shutdown(struct platform_device *pdev)
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{
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struct mt7621_wdt_data *drvdata = platform_get_drvdata(pdev);
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mt7621_wdt_stop(&drvdata->wdt);
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}
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static const struct of_device_id mt7621_wdt_match[] = {
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{ .compatible = "mediatek,mt7621-wdt" },
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{},
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};
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MODULE_DEVICE_TABLE(of, mt7621_wdt_match);
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static struct platform_driver mt7621_wdt_driver = {
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.probe = mt7621_wdt_probe,
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.shutdown = mt7621_wdt_shutdown,
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.driver = {
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.name = KBUILD_MODNAME,
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.of_match_table = mt7621_wdt_match,
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},
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};
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module_platform_driver(mt7621_wdt_driver);
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MODULE_DESCRIPTION("MediaTek MT762x hardware watchdog driver");
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MODULE_AUTHOR("John Crispin <john@phrozen.org");
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MODULE_LICENSE("GPL v2");
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