2020-03-02 16:04:46 -05:00
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// SPDX-License-Identifier: GPL-2.0
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2021-10-15 12:48:08 -04:00
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/*
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* Copyright (C) 2020-2021 NVIDIA CORPORATION & AFFILIATES
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*/
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2020-03-02 16:04:46 -05:00
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#include <linux/bitfield.h>
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#include <linux/bitops.h>
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#include <linux/device.h>
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#include <linux/gpio/driver.h>
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2021-10-15 12:48:08 -04:00
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#include <linux/interrupt.h>
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2020-03-02 16:04:46 -05:00
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <linux/kernel.h>
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2021-08-16 07:59:49 -04:00
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#include <linux/mod_devicetable.h>
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2020-03-02 16:04:46 -05:00
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/pm.h>
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#include <linux/resource.h>
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2023-03-09 02:46:00 -05:00
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#include <linux/seq_file.h>
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2020-03-02 16:04:46 -05:00
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#include <linux/spinlock.h>
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#include <linux/types.h>
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/*
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* There are 3 YU GPIO blocks:
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* gpio[0]: HOST_GPIO0->HOST_GPIO31
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* gpio[1]: HOST_GPIO32->HOST_GPIO63
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* gpio[2]: HOST_GPIO64->HOST_GPIO69
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*/
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#define MLXBF2_GPIO_MAX_PINS_PER_BLOCK 32
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/*
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* arm_gpio_lock register:
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* bit[31] lock status: active if set
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* bit[15:0] set lock
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* The lock is enabled only if 0xd42f is written to this field
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*/
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#define YU_ARM_GPIO_LOCK_ADDR 0x2801088
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#define YU_ARM_GPIO_LOCK_SIZE 0x8
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#define YU_LOCK_ACTIVE_BIT(val) (val >> 31)
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#define YU_ARM_GPIO_LOCK_ACQUIRE 0xd42f
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#define YU_ARM_GPIO_LOCK_RELEASE 0x0
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/*
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* gpio[x] block registers and their offset
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*/
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#define YU_GPIO_DATAIN 0x04
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#define YU_GPIO_MODE1 0x08
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#define YU_GPIO_MODE0 0x0c
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#define YU_GPIO_DATASET 0x14
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#define YU_GPIO_DATACLEAR 0x18
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2021-10-15 12:48:08 -04:00
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#define YU_GPIO_CAUSE_RISE_EN 0x44
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#define YU_GPIO_CAUSE_FALL_EN 0x48
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2020-03-02 16:04:46 -05:00
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#define YU_GPIO_MODE1_CLEAR 0x50
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#define YU_GPIO_MODE0_SET 0x54
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#define YU_GPIO_MODE0_CLEAR 0x58
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2021-10-15 12:48:08 -04:00
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#define YU_GPIO_CAUSE_OR_CAUSE_EVTEN0 0x80
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#define YU_GPIO_CAUSE_OR_EVTEN0 0x94
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#define YU_GPIO_CAUSE_OR_CLRCAUSE 0x98
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2020-03-02 16:04:46 -05:00
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struct mlxbf2_gpio_context_save_regs {
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u32 gpio_mode0;
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u32 gpio_mode1;
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};
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/* BlueField-2 gpio block context structure. */
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struct mlxbf2_gpio_context {
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struct gpio_chip gc;
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/* YU GPIO blocks address */
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void __iomem *gpio_io;
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struct device *dev;
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2020-03-02 16:04:46 -05:00
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struct mlxbf2_gpio_context_save_regs *csave_regs;
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};
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/* BlueField-2 gpio shared structure. */
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struct mlxbf2_gpio_param {
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void __iomem *io;
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struct resource *res;
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struct mutex *lock;
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};
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2021-08-16 07:59:51 -04:00
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static struct resource yu_arm_gpio_lock_res =
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DEFINE_RES_MEM_NAMED(YU_ARM_GPIO_LOCK_ADDR, YU_ARM_GPIO_LOCK_SIZE, "YU_ARM_GPIO_LOCK");
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2020-03-02 16:04:46 -05:00
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static DEFINE_MUTEX(yu_arm_gpio_lock_mutex);
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static struct mlxbf2_gpio_param yu_arm_gpio_lock_param = {
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.res = &yu_arm_gpio_lock_res,
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.lock = &yu_arm_gpio_lock_mutex,
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};
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/* Request memory region and map yu_arm_gpio_lock resource */
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static int mlxbf2_gpio_get_lock_res(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct resource *res;
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resource_size_t size;
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int ret = 0;
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mutex_lock(yu_arm_gpio_lock_param.lock);
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/* Check if the memory map already exists */
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if (yu_arm_gpio_lock_param.io)
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goto exit;
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res = yu_arm_gpio_lock_param.res;
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size = resource_size(res);
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if (!devm_request_mem_region(dev, res->start, size, res->name)) {
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ret = -EFAULT;
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goto exit;
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}
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yu_arm_gpio_lock_param.io = devm_ioremap(dev, res->start, size);
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2020-04-27 07:08:29 -04:00
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if (!yu_arm_gpio_lock_param.io)
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ret = -ENOMEM;
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2020-03-02 16:04:46 -05:00
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exit:
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mutex_unlock(yu_arm_gpio_lock_param.lock);
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return ret;
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}
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/*
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* Acquire the YU arm_gpio_lock to be able to change the direction
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* mode. If the lock_active bit is already set, return an error.
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*/
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static int mlxbf2_gpio_lock_acquire(struct mlxbf2_gpio_context *gs)
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{
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u32 arm_gpio_lock_val;
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mutex_lock(yu_arm_gpio_lock_param.lock);
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2022-04-18 21:28:10 -04:00
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raw_spin_lock(&gs->gc.bgpio_lock);
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2020-03-02 16:04:46 -05:00
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arm_gpio_lock_val = readl(yu_arm_gpio_lock_param.io);
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/*
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* When lock active bit[31] is set, ModeX is write enabled
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*/
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if (YU_LOCK_ACTIVE_BIT(arm_gpio_lock_val)) {
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2022-04-18 21:28:10 -04:00
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raw_spin_unlock(&gs->gc.bgpio_lock);
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2020-05-20 21:57:13 -04:00
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mutex_unlock(yu_arm_gpio_lock_param.lock);
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2020-03-02 16:04:46 -05:00
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return -EINVAL;
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}
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writel(YU_ARM_GPIO_LOCK_ACQUIRE, yu_arm_gpio_lock_param.io);
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return 0;
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}
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/*
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* Release the YU arm_gpio_lock after changing the direction mode.
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*/
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static void mlxbf2_gpio_lock_release(struct mlxbf2_gpio_context *gs)
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2020-06-30 09:33:45 -04:00
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__releases(&gs->gc.bgpio_lock)
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__releases(yu_arm_gpio_lock_param.lock)
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2020-03-02 16:04:46 -05:00
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{
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writel(YU_ARM_GPIO_LOCK_RELEASE, yu_arm_gpio_lock_param.io);
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2022-04-18 21:28:10 -04:00
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raw_spin_unlock(&gs->gc.bgpio_lock);
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2020-05-20 21:57:13 -04:00
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mutex_unlock(yu_arm_gpio_lock_param.lock);
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2020-03-02 16:04:46 -05:00
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}
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/*
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* mode0 and mode1 are both locked by the gpio_lock field.
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*
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* Together, mode0 and mode1 define the gpio Mode dependeing also
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* on Reg_DataOut.
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*
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* {mode1,mode0}:{Reg_DataOut=0,Reg_DataOut=1}->{DataOut=0,DataOut=1}
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*
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* {0,0}:Reg_DataOut{0,1}->{Z,Z} Input PAD
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* {0,1}:Reg_DataOut{0,1}->{0,1} Full drive Output PAD
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* {1,0}:Reg_DataOut{0,1}->{0,Z} 0-set PAD to low, 1-float
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* {1,1}:Reg_DataOut{0,1}->{Z,1} 0-float, 1-set PAD to high
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*/
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/*
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* Set input direction:
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* {mode1,mode0} = {0,0}
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*/
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static int mlxbf2_gpio_direction_input(struct gpio_chip *chip,
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unsigned int offset)
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{
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struct mlxbf2_gpio_context *gs = gpiochip_get_data(chip);
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int ret;
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/*
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* Although the arm_gpio_lock was set in the probe function, check again
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* if it is still enabled to be able to write to the ModeX registers.
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*/
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ret = mlxbf2_gpio_lock_acquire(gs);
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if (ret < 0)
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return ret;
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writel(BIT(offset), gs->gpio_io + YU_GPIO_MODE0_CLEAR);
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writel(BIT(offset), gs->gpio_io + YU_GPIO_MODE1_CLEAR);
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mlxbf2_gpio_lock_release(gs);
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return ret;
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}
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/*
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* Set output direction:
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* {mode1,mode0} = {0,1}
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*/
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static int mlxbf2_gpio_direction_output(struct gpio_chip *chip,
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unsigned int offset,
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int value)
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{
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struct mlxbf2_gpio_context *gs = gpiochip_get_data(chip);
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int ret = 0;
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/*
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* Although the arm_gpio_lock was set in the probe function,
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* check again it is still enabled to be able to write to the
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* ModeX registers.
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*/
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ret = mlxbf2_gpio_lock_acquire(gs);
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if (ret < 0)
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return ret;
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writel(BIT(offset), gs->gpio_io + YU_GPIO_MODE1_CLEAR);
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writel(BIT(offset), gs->gpio_io + YU_GPIO_MODE0_SET);
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mlxbf2_gpio_lock_release(gs);
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return ret;
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}
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2021-10-15 12:48:08 -04:00
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static void mlxbf2_gpio_irq_enable(struct irq_data *irqd)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
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struct mlxbf2_gpio_context *gs = gpiochip_get_data(gc);
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int offset = irqd_to_hwirq(irqd);
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unsigned long flags;
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u32 val;
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2023-03-09 02:46:00 -05:00
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gpiochip_enable_irq(gc, irqd_to_hwirq(irqd));
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2022-04-18 21:28:10 -04:00
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raw_spin_lock_irqsave(&gs->gc.bgpio_lock, flags);
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2021-10-15 12:48:08 -04:00
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val = readl(gs->gpio_io + YU_GPIO_CAUSE_OR_CLRCAUSE);
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val |= BIT(offset);
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writel(val, gs->gpio_io + YU_GPIO_CAUSE_OR_CLRCAUSE);
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val = readl(gs->gpio_io + YU_GPIO_CAUSE_OR_EVTEN0);
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val |= BIT(offset);
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writel(val, gs->gpio_io + YU_GPIO_CAUSE_OR_EVTEN0);
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2022-04-18 21:28:10 -04:00
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raw_spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags);
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2021-10-15 12:48:08 -04:00
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}
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static void mlxbf2_gpio_irq_disable(struct irq_data *irqd)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
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struct mlxbf2_gpio_context *gs = gpiochip_get_data(gc);
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int offset = irqd_to_hwirq(irqd);
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unsigned long flags;
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u32 val;
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2022-04-18 21:28:10 -04:00
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raw_spin_lock_irqsave(&gs->gc.bgpio_lock, flags);
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2021-10-15 12:48:08 -04:00
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val = readl(gs->gpio_io + YU_GPIO_CAUSE_OR_EVTEN0);
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val &= ~BIT(offset);
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writel(val, gs->gpio_io + YU_GPIO_CAUSE_OR_EVTEN0);
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2022-04-18 21:28:10 -04:00
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raw_spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags);
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2023-03-09 02:46:00 -05:00
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gpiochip_disable_irq(gc, irqd_to_hwirq(irqd));
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2021-10-15 12:48:08 -04:00
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}
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static irqreturn_t mlxbf2_gpio_irq_handler(int irq, void *ptr)
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{
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struct mlxbf2_gpio_context *gs = ptr;
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struct gpio_chip *gc = &gs->gc;
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unsigned long pending;
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u32 level;
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pending = readl(gs->gpio_io + YU_GPIO_CAUSE_OR_CAUSE_EVTEN0);
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writel(pending, gs->gpio_io + YU_GPIO_CAUSE_OR_CLRCAUSE);
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2022-09-19 08:45:18 -04:00
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for_each_set_bit(level, &pending, gc->ngpio)
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generic_handle_domain_irq_safe(gc->irq.domain, level);
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2021-10-15 12:48:08 -04:00
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return IRQ_RETVAL(pending);
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}
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static int
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mlxbf2_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
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struct mlxbf2_gpio_context *gs = gpiochip_get_data(gc);
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int offset = irqd_to_hwirq(irqd);
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unsigned long flags;
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bool fall = false;
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bool rise = false;
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u32 val;
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switch (type & IRQ_TYPE_SENSE_MASK) {
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case IRQ_TYPE_EDGE_BOTH:
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fall = true;
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rise = true;
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break;
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case IRQ_TYPE_EDGE_RISING:
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rise = true;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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fall = true;
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break;
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default:
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return -EINVAL;
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}
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2022-04-18 21:28:10 -04:00
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raw_spin_lock_irqsave(&gs->gc.bgpio_lock, flags);
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2021-10-15 12:48:08 -04:00
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if (fall) {
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val = readl(gs->gpio_io + YU_GPIO_CAUSE_FALL_EN);
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val |= BIT(offset);
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writel(val, gs->gpio_io + YU_GPIO_CAUSE_FALL_EN);
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}
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if (rise) {
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val = readl(gs->gpio_io + YU_GPIO_CAUSE_RISE_EN);
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val |= BIT(offset);
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writel(val, gs->gpio_io + YU_GPIO_CAUSE_RISE_EN);
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|
|
|
}
|
2022-04-18 21:28:10 -04:00
|
|
|
raw_spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags);
|
2021-10-15 12:48:08 -04:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2023-03-09 02:46:00 -05:00
|
|
|
static void mlxbf2_gpio_irq_print_chip(struct irq_data *irqd,
|
|
|
|
struct seq_file *p)
|
|
|
|
{
|
|
|
|
struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
|
|
|
|
struct mlxbf2_gpio_context *gs = gpiochip_get_data(gc);
|
|
|
|
|
|
|
|
seq_printf(p, dev_name(gs->dev));
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct irq_chip mlxbf2_gpio_irq_chip = {
|
|
|
|
.irq_set_type = mlxbf2_gpio_irq_set_type,
|
|
|
|
.irq_enable = mlxbf2_gpio_irq_enable,
|
|
|
|
.irq_disable = mlxbf2_gpio_irq_disable,
|
|
|
|
.irq_print_chip = mlxbf2_gpio_irq_print_chip,
|
|
|
|
.flags = IRQCHIP_IMMUTABLE,
|
|
|
|
GPIOCHIP_IRQ_RESOURCE_HELPERS,
|
|
|
|
};
|
|
|
|
|
2020-03-02 16:04:46 -05:00
|
|
|
/* BlueField-2 GPIO driver initialization routine. */
|
|
|
|
static int
|
|
|
|
mlxbf2_gpio_probe(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct mlxbf2_gpio_context *gs;
|
|
|
|
struct device *dev = &pdev->dev;
|
2021-10-15 12:48:08 -04:00
|
|
|
struct gpio_irq_chip *girq;
|
2020-03-02 16:04:46 -05:00
|
|
|
struct gpio_chip *gc;
|
|
|
|
unsigned int npins;
|
2021-10-15 12:48:08 -04:00
|
|
|
const char *name;
|
|
|
|
int ret, irq;
|
|
|
|
|
|
|
|
name = dev_name(dev);
|
2020-03-02 16:04:46 -05:00
|
|
|
|
|
|
|
gs = devm_kzalloc(dev, sizeof(*gs), GFP_KERNEL);
|
|
|
|
if (!gs)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
2023-03-09 02:46:00 -05:00
|
|
|
gs->dev = dev;
|
|
|
|
|
2020-03-02 16:04:46 -05:00
|
|
|
/* YU GPIO block address */
|
2021-08-16 07:59:50 -04:00
|
|
|
gs->gpio_io = devm_platform_ioremap_resource(pdev, 0);
|
|
|
|
if (IS_ERR(gs->gpio_io))
|
|
|
|
return PTR_ERR(gs->gpio_io);
|
2020-03-02 16:04:46 -05:00
|
|
|
|
|
|
|
ret = mlxbf2_gpio_get_lock_res(pdev);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "Failed to get yu_arm_gpio_lock resource\n");
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (device_property_read_u32(dev, "npins", &npins))
|
|
|
|
npins = MLXBF2_GPIO_MAX_PINS_PER_BLOCK;
|
|
|
|
|
|
|
|
gc = &gs->gc;
|
|
|
|
|
|
|
|
ret = bgpio_init(gc, dev, 4,
|
|
|
|
gs->gpio_io + YU_GPIO_DATAIN,
|
|
|
|
gs->gpio_io + YU_GPIO_DATASET,
|
|
|
|
gs->gpio_io + YU_GPIO_DATACLEAR,
|
|
|
|
NULL,
|
|
|
|
NULL,
|
|
|
|
0);
|
|
|
|
|
2021-10-22 09:44:38 -04:00
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "bgpio_init failed\n");
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2020-03-02 16:04:46 -05:00
|
|
|
gc->direction_input = mlxbf2_gpio_direction_input;
|
|
|
|
gc->direction_output = mlxbf2_gpio_direction_output;
|
|
|
|
gc->ngpio = npins;
|
|
|
|
gc->owner = THIS_MODULE;
|
|
|
|
|
2021-10-15 12:48:08 -04:00
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
|
|
if (irq >= 0) {
|
|
|
|
girq = &gs->gc.irq;
|
2023-03-09 02:46:00 -05:00
|
|
|
gpio_irq_chip_set_chip(girq, &mlxbf2_gpio_irq_chip);
|
2021-10-15 12:48:08 -04:00
|
|
|
girq->handler = handle_simple_irq;
|
|
|
|
girq->default_type = IRQ_TYPE_NONE;
|
|
|
|
/* This will let us handle the parent IRQ in the driver */
|
|
|
|
girq->num_parents = 0;
|
|
|
|
girq->parents = NULL;
|
|
|
|
girq->parent_handler = NULL;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Directly request the irq here instead of passing
|
|
|
|
* a flow-handler because the irq is shared.
|
|
|
|
*/
|
|
|
|
ret = devm_request_irq(dev, irq, mlxbf2_gpio_irq_handler,
|
|
|
|
IRQF_SHARED, name, gs);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "failed to request IRQ");
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-03-02 16:04:46 -05:00
|
|
|
platform_set_drvdata(pdev, gs);
|
|
|
|
|
|
|
|
ret = devm_gpiochip_add_data(dev, &gs->gc, gs);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "Failed adding memory mapped gpiochip\n");
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2021-08-16 07:59:48 -04:00
|
|
|
static int __maybe_unused mlxbf2_gpio_suspend(struct device *dev)
|
2020-03-02 16:04:46 -05:00
|
|
|
{
|
2021-08-16 07:59:48 -04:00
|
|
|
struct mlxbf2_gpio_context *gs = dev_get_drvdata(dev);
|
2020-03-02 16:04:46 -05:00
|
|
|
|
|
|
|
gs->csave_regs->gpio_mode0 = readl(gs->gpio_io +
|
|
|
|
YU_GPIO_MODE0);
|
|
|
|
gs->csave_regs->gpio_mode1 = readl(gs->gpio_io +
|
|
|
|
YU_GPIO_MODE1);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2021-08-16 07:59:48 -04:00
|
|
|
static int __maybe_unused mlxbf2_gpio_resume(struct device *dev)
|
2020-03-02 16:04:46 -05:00
|
|
|
{
|
2021-08-16 07:59:48 -04:00
|
|
|
struct mlxbf2_gpio_context *gs = dev_get_drvdata(dev);
|
2020-03-02 16:04:46 -05:00
|
|
|
|
|
|
|
writel(gs->csave_regs->gpio_mode0, gs->gpio_io +
|
|
|
|
YU_GPIO_MODE0);
|
|
|
|
writel(gs->csave_regs->gpio_mode1, gs->gpio_io +
|
|
|
|
YU_GPIO_MODE1);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
2021-08-16 07:59:48 -04:00
|
|
|
static SIMPLE_DEV_PM_OPS(mlxbf2_pm_ops, mlxbf2_gpio_suspend, mlxbf2_gpio_resume);
|
2020-03-02 16:04:46 -05:00
|
|
|
|
2020-06-30 09:33:44 -04:00
|
|
|
static const struct acpi_device_id __maybe_unused mlxbf2_gpio_acpi_match[] = {
|
2020-03-02 16:04:46 -05:00
|
|
|
{ "MLNXBF22", 0 },
|
|
|
|
{},
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(acpi, mlxbf2_gpio_acpi_match);
|
|
|
|
|
|
|
|
static struct platform_driver mlxbf2_gpio_driver = {
|
|
|
|
.driver = {
|
|
|
|
.name = "mlxbf2_gpio",
|
2021-08-16 07:59:49 -04:00
|
|
|
.acpi_match_table = mlxbf2_gpio_acpi_match,
|
2021-08-16 07:59:48 -04:00
|
|
|
.pm = &mlxbf2_pm_ops,
|
2020-03-02 16:04:46 -05:00
|
|
|
},
|
|
|
|
.probe = mlxbf2_gpio_probe,
|
|
|
|
};
|
|
|
|
|
|
|
|
module_platform_driver(mlxbf2_gpio_driver);
|
|
|
|
|
|
|
|
MODULE_DESCRIPTION("Mellanox BlueField-2 GPIO Driver");
|
2021-10-15 12:48:08 -04:00
|
|
|
MODULE_AUTHOR("Asmaa Mnebhi <asmaa@nvidia.com>");
|
2020-03-02 16:04:46 -05:00
|
|
|
MODULE_LICENSE("GPL v2");
|