2022-05-31 06:04:11 -04:00
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* LoongArch cacheinfo support
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*
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* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
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*/
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#include <linux/cacheinfo.h>
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LoongArch: Refactor cache probe and flush methods
Current cache probe and flush methods have some drawbacks:
1, Assume there are 3 cache levels and only 3 levels;
2, Assume L1 = I + D, L2 = V, L3 = S, V is exclusive, S is inclusive.
However, the fact is I + D, I + D + V, I + D + S and I + D + V + S are
all valid. So, refactor the cache probe and flush methods to adapt more
types of cache hierarchy.
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
2022-10-12 04:36:14 -04:00
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#include <linux/topology.h>
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2022-07-13 06:00:41 -04:00
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#include <asm/bootinfo.h>
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#include <asm/cpu-info.h>
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2022-05-31 06:04:11 -04:00
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int init_cache_level(unsigned int cpu)
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{
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LoongArch: Refactor cache probe and flush methods
Current cache probe and flush methods have some drawbacks:
1, Assume there are 3 cache levels and only 3 levels;
2, Assume L1 = I + D, L2 = V, L3 = S, V is exclusive, S is inclusive.
However, the fact is I + D, I + D + V, I + D + S and I + D + V + S are
all valid. So, refactor the cache probe and flush methods to adapt more
types of cache hierarchy.
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
2022-10-12 04:36:14 -04:00
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int cache_present = current_cpu_data.cache_leaves_present;
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2022-05-31 06:04:11 -04:00
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struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
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LoongArch: Refactor cache probe and flush methods
Current cache probe and flush methods have some drawbacks:
1, Assume there are 3 cache levels and only 3 levels;
2, Assume L1 = I + D, L2 = V, L3 = S, V is exclusive, S is inclusive.
However, the fact is I + D, I + D + V, I + D + S and I + D + V + S are
all valid. So, refactor the cache probe and flush methods to adapt more
types of cache hierarchy.
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
2022-10-12 04:36:14 -04:00
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this_cpu_ci->num_levels =
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current_cpu_data.cache_leaves[cache_present - 1].level;
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this_cpu_ci->num_leaves = cache_present;
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2022-05-31 06:04:11 -04:00
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return 0;
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}
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static inline bool cache_leaves_are_shared(struct cacheinfo *this_leaf,
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struct cacheinfo *sib_leaf)
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{
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LoongArch: Refactor cache probe and flush methods
Current cache probe and flush methods have some drawbacks:
1, Assume there are 3 cache levels and only 3 levels;
2, Assume L1 = I + D, L2 = V, L3 = S, V is exclusive, S is inclusive.
However, the fact is I + D, I + D + V, I + D + S and I + D + V + S are
all valid. So, refactor the cache probe and flush methods to adapt more
types of cache hierarchy.
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
2022-10-12 04:36:14 -04:00
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return (!(*(unsigned char *)(this_leaf->priv) & CACHE_PRIVATE)
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&& !(*(unsigned char *)(sib_leaf->priv) & CACHE_PRIVATE));
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2022-05-31 06:04:11 -04:00
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}
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static void cache_cpumap_setup(unsigned int cpu)
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{
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unsigned int index;
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LoongArch: Refactor cache probe and flush methods
Current cache probe and flush methods have some drawbacks:
1, Assume there are 3 cache levels and only 3 levels;
2, Assume L1 = I + D, L2 = V, L3 = S, V is exclusive, S is inclusive.
However, the fact is I + D, I + D + V, I + D + S and I + D + V + S are
all valid. So, refactor the cache probe and flush methods to adapt more
types of cache hierarchy.
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
2022-10-12 04:36:14 -04:00
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struct cacheinfo *this_leaf, *sib_leaf;
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struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
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2022-05-31 06:04:11 -04:00
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for (index = 0; index < this_cpu_ci->num_leaves; index++) {
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unsigned int i;
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this_leaf = this_cpu_ci->info_list + index;
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/* skip if shared_cpu_map is already populated */
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if (!cpumask_empty(&this_leaf->shared_cpu_map))
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continue;
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cpumask_set_cpu(cpu, &this_leaf->shared_cpu_map);
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for_each_online_cpu(i) {
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struct cpu_cacheinfo *sib_cpu_ci = get_cpu_cacheinfo(i);
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LoongArch: Refactor cache probe and flush methods
Current cache probe and flush methods have some drawbacks:
1, Assume there are 3 cache levels and only 3 levels;
2, Assume L1 = I + D, L2 = V, L3 = S, V is exclusive, S is inclusive.
However, the fact is I + D, I + D + V, I + D + S and I + D + V + S are
all valid. So, refactor the cache probe and flush methods to adapt more
types of cache hierarchy.
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
2022-10-12 04:36:14 -04:00
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if (i == cpu || !sib_cpu_ci->info_list ||
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(cpu_to_node(i) != cpu_to_node(cpu)))
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continue;
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2022-05-31 06:04:11 -04:00
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sib_leaf = sib_cpu_ci->info_list + index;
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if (cache_leaves_are_shared(this_leaf, sib_leaf)) {
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cpumask_set_cpu(cpu, &sib_leaf->shared_cpu_map);
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cpumask_set_cpu(i, &this_leaf->shared_cpu_map);
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}
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}
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}
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}
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int populate_cache_leaves(unsigned int cpu)
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{
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LoongArch: Refactor cache probe and flush methods
Current cache probe and flush methods have some drawbacks:
1, Assume there are 3 cache levels and only 3 levels;
2, Assume L1 = I + D, L2 = V, L3 = S, V is exclusive, S is inclusive.
However, the fact is I + D, I + D + V, I + D + S and I + D + V + S are
all valid. So, refactor the cache probe and flush methods to adapt more
types of cache hierarchy.
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
2022-10-12 04:36:14 -04:00
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int i, cache_present = current_cpu_data.cache_leaves_present;
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2022-05-31 06:04:11 -04:00
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struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
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struct cacheinfo *this_leaf = this_cpu_ci->info_list;
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LoongArch: Refactor cache probe and flush methods
Current cache probe and flush methods have some drawbacks:
1, Assume there are 3 cache levels and only 3 levels;
2, Assume L1 = I + D, L2 = V, L3 = S, V is exclusive, S is inclusive.
However, the fact is I + D, I + D + V, I + D + S and I + D + V + S are
all valid. So, refactor the cache probe and flush methods to adapt more
types of cache hierarchy.
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
2022-10-12 04:36:14 -04:00
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struct cache_desc *cd, *cdesc = current_cpu_data.cache_leaves;
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for (i = 0; i < cache_present; i++) {
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cd = cdesc + i;
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this_leaf->type = cd->type;
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this_leaf->level = cd->level;
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this_leaf->coherency_line_size = cd->linesz;
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this_leaf->number_of_sets = cd->sets;
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this_leaf->ways_of_associativity = cd->ways;
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this_leaf->size = cd->linesz * cd->sets * cd->ways;
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this_leaf->priv = &cd->flags;
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this_leaf++;
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2022-05-31 06:04:11 -04:00
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}
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cache_cpumap_setup(cpu);
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this_cpu_ci->cpu_map_populated = true;
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return 0;
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}
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