forked from Mirrors/freeswitch
dced381e66
git-svn-id: http://svn.freeswitch.org/svn/freeswitch/trunk@3759 d0543943-73ff-0310-b7d9-9358b9ac24b2
132 lines
4.2 KiB
C
132 lines
4.2 KiB
C
/* Copyright (C) 2005 Analog Devices */
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/**
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@file lpc_bfin.h
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@author Jean-Marc Valin
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@brief Functions for LPC (Linear Prediction Coefficients) analysis (Blackfin version)
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*/
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/*
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions
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are met:
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- Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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- Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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- Neither the name of the Xiph.org Foundation nor the names of its
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contributors may be used to endorse or promote products derived from
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this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR
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CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#define OVERRIDE_SPEEX_AUTOCORR
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void _spx_autocorr(
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const spx_word16_t *x, /* in: [0...n-1] samples x */
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spx_word16_t *ac, /* out: [0...lag-1] ac values */
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int lag,
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int n
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)
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{
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spx_word32_t d;
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const spx_word16_t *xs;
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int i, j;
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spx_word32_t ac0=1;
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spx_word32_t ac32[11], *ac32top;
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int shift, ac_shift;
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ac32top = ac32+lag-1;
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int lag_1, N_lag;
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int nshift;
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lag_1 = lag-1;
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N_lag = n-lag_1;
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for (j=0;j<n;j++)
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ac0 = ADD32(ac0,SHR32(MULT16_16(x[j],x[j]),8));
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ac0 = ADD32(ac0,n);
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shift = 8;
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while (shift && ac0<0x40000000)
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{
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shift--;
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ac0 <<= 1;
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}
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ac_shift = 18;
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while (ac_shift && ac0<0x40000000)
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{
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ac_shift--;
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ac0 <<= 1;
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}
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xs = x+lag-1;
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nshift = -shift;
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__asm__ __volatile__
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(
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"P2 = %0;\n\t"
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"I0 = P2;\n\t" /* x in I0 */
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"B0 = P2;\n\t" /* x in B0 */
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"R0 = %3;\n\t" /* len in R0 */
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"P3 = %3;\n\t" /* len in R0 */
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"P4 = %4;\n\t" /* nb_pitch in R0 */
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"R1 = R0 << 1;\n\t" /* number of bytes in x */
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"L0 = R1;\n\t"
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"P0 = %1;\n\t"
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"P1 = %2;\n\t"
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"B1 = P1;\n\t"
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"R4 = %5;\n\t"
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"L1 = 0;\n\t" /*Disable looping on I1*/
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"r0 = [I0++];\n\t"
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"R2 = 0;R3=0;"
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"LOOP pitch%= LC0 = P4 >> 1;\n\t"
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"LOOP_BEGIN pitch%=;\n\t"
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"I1 = P0;\n\t"
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"A1 = A0 = 0;\n\t"
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"R1 = [I1++];\n\t"
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"LOOP inner_prod%= LC1 = P3 >> 1;\n\t"
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"LOOP_BEGIN inner_prod%=;\n\t"
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"A1 += R0.L*R1.H, A0 += R0.L*R1.L (IS) || R1.L = W[I1++];\n\t"
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"A1 += R0.H*R1.L, A0 += R0.H*R1.H (IS) || R1.H = W[I1++] || R0 = [I0++];\n\t"
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"LOOP_END inner_prod%=;\n\t"
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"A0 = ASHIFT A0 by R4.L;\n\t"
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"A1 = ASHIFT A1 by R4.L;\n\t"
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"R2 = A0, R3 = A1;\n\t"
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"[P1--] = R2;\n\t"
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"[P1--] = R3;\n\t"
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"P0 += 4;\n\t"
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"LOOP_END pitch%=;\n\t"
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: : "m" (xs), "m" (x), "m" (ac32top), "m" (N_lag), "m" (lag_1), "m" (nshift)
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: "A0", "A1", "P0", "P1", "P2", "P3", "P4", "R0", "R1", "R2", "R3", "R4", "I0", "I1", "L0", "L1", "B0", "B1", "memory"
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);
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d=0;
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for (j=0;j<n;j++)
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{
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d = ADD32(d,SHR32(MULT16_16(x[j],x[j]), shift));
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}
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ac32[0] = d;
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for (i=0;i<lag;i++)
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{
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d=0;
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for (j=i;j<lag_1;j++)
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{
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d = ADD32(d,SHR32(MULT16_16(x[j],x[j-i]), shift));
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}
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if (i)
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ac32[i] += d;
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ac[i] = SHR32(ac32[i], ac_shift);
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}
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}
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